公开(公告)号：US20250112102A1

公开(公告)日：2025-04-03

申请号：US18980281

申请日：2024-12-13

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Su-Jen Sung ,  Jr-Hung Li ,  Tze-Liang Lee

IPC: H01L23/31 ,  H01L21/56 ,  H01L23/00 ,  H01L23/29 ,  H01L23/538 ,  H01L25/10

Abstract: A method includes bonding a first wafer to a second wafer, performing a trimming process on the first wafer, and depositing a sidewall protection layer contacting a sidewall of the first wafer. The depositing the sidewall protection layer includes depositing a high-density material in contact with the sidewall of the first wafer. The sidewall protection layer has a density higher than a density of silicon oxide. The method further includes removing a horizontal portion of the sidewall protection layer that overlaps the first wafer, and forming an interconnect structure over the first wafer. The interconnect structure is electrically connected to integrated circuit devices in the first wafer.

公开(公告)号：US12266686B2

公开(公告)日：2025-04-01

申请号：US17850356

申请日：2022-06-27

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Jhon Jhy Liaw

IPC: H01L29/66 ,  H01L29/06 ,  H01L29/417 ,  H01L29/78

Abstract: A semiconductor device includes a substrate, a p-type well over the substrate and having a p-type anti-punch-through (APT) layer, an n-type source feature and an n-type drain feature over the p-type APT layer, and multiple first channel layers suspended over the p-type APT layer and connecting the n-type source feature to the n-type drain feature. The multiple first channel layers are vertically stacked one over another and are undoped. The semiconductor device further includes a high-k metal gate wrapping around each of the first channel layers, a first source contact disposed over and electrically coupled to the n-type source feature, and a drain contact disposed over and electrically coupled to the n-type drain feature. A bottom surface of the n-type source feature is about 5 nm to about 25 nm below an interface between the high-k metal gate and the p-type APT layer.

公开(公告)号：US12266573B2

公开(公告)日：2025-04-01

申请号：US17483043

申请日：2021-09-23

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Yi Chen Ho ,  Yiting Chang ,  Chi-Hsun Lin ,  Zheng-Yang Pan

IPC: H01L21/8234 ,  H01L21/02 ,  H01L21/762 ,  H01L27/088

Abstract: In an embodiment, a device includes: an isolation region on a substrate; a first semiconductor fin protruding above the isolation region; a second semiconductor fin protruding above the isolation region; and a dielectric fin between the first semiconductor fin and the second semiconductor fin, the dielectric fin protruding above the isolation region, the dielectric fin including: a first layer including a first dielectric material having a first carbon concentration; and a second layer on the first layer, the second layer including a second dielectric material having a second carbon concentration, the second carbon concentration greater than the first carbon concentration.

公开(公告)号：US12266572B2

公开(公告)日：2025-04-01

申请号：US17124017

申请日：2020-12-16

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Shahaji B. More

IPC: H01L21/8234 ,  H01L21/762 ,  H01L29/417 ,  H01L29/66 ,  H01L29/78

Abstract: A method includes forming a semiconductor fin, forming a gate stack on the semiconductor fin, and a gate spacer on a sidewall of the gate stack. The method further includes recessing the semiconductor fin to form a recess, performing a first epitaxy process to grow a first epitaxy semiconductor layer in the recess, wherein the first epitaxy semiconductor layer, and performing a second epitaxy process to grow an embedded stressor extending into the recess. The embedded stressor has a top portion higher than a top surface of the semiconductor fin, with the top portion having a first sidewall contacting a second sidewall of the gate spacer, and with the sidewall having a bottom end level with the top surface of the semiconductor fin. The embedded spacer has a bottom portion lower than the top surface of the semiconductor fin.

公开(公告)号：US12266566B2

公开(公告)日：2025-04-01

申请号：US18447084

申请日：2023-08-09

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chun-Yuan Chen ,  Shih-Chuan Chiu ,  Jia-Chuan You ,  Chia-Hao Chang ,  Tien-Lu Lin ,  Yu-Ming Lin

IPC: H01L23/522 ,  H01L21/321 ,  H01L21/768 ,  H01L23/528 ,  H01L23/532

Abstract: A method includes forming a first conductive feature on a substrate, forming a via that contacts the first conductive feature, the via comprising a conductive material, performing a Chemical Mechanical Polishing (CMP) process to a top surface of the via, depositing an Interlayer Dielectric (ILD) layer on the via, forming a trench within the ILD layer to expose the via, and filling the trench with a second conductive feature that contacts the via, the second conductive feature comprising a same material as the conductive material.

公开(公告)号：US12266526B2

公开(公告)日：2025-04-01

申请号：US18480378

申请日：2023-10-03

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Martin Christopher Holland

IPC: H01L29/00 ,  C30B19/10 ,  C30B19/12 ,  C30B29/06 ,  C30B29/08 ,  H01L21/02 ,  H01L21/762 ,  H01L29/04 ,  H01L29/06 ,  H01L29/78

Abstract: A semiconductor device is provided. The semiconductor device includes a template layer disposed over a substrate and having a trench therein, a buffer structure disposed over a bottom surface of the trench and comprising a metal oxide, a single crystal semiconductor structure disposed within the trench and over the buffer structure and a gate structure disposed over a channel region of the single crystal semiconductor structure.

公开(公告)号：US20250105174A1

公开(公告)日：2025-03-27

申请号：US18416410

申请日：2024-01-18

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chen Hua Huang ,  Cheng-Hsien Hsieh ,  Li-Han Hsu

IPC: H01L23/58 ,  H01L21/768 ,  H01L23/00 ,  H01L23/31 ,  H01L23/48

Abstract: A semiconductor device and method of manufacture are provided wherein semiconductor devices are attached over a semiconductor substrate. A seal ring within the semiconductor device is extended to include a first bond metal within a bonding layer and bonded to a second bond metal over the semiconductor substrate. Such a seal ring provided a more complete protection from cracking and delamination.

公开(公告)号：US20250105172A1

公开(公告)日：2025-03-27

申请号：US18543799

申请日：2023-12-18

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Kuo-Chiang Ting ,  Sung-Feng Yeh ,  Ta Hao Sung ,  Ming-Zhi Yang ,  Gao-Long Wu

IPC: H01L23/00 ,  H01L23/538

Abstract: An embodiment includes a method including forming a first interconnect structure over a first substrate, the first interconnect structure including dielectric layers and metallization patterns therein. The method also includes forming a redistribution via and a redistribution pad over the first interconnect structure, the redistribution via and the redistribution pad being electrically coupled to at least one of the metallization patterns of the first interconnect structure, the redistribution via and the redistribution pad having a same material composition. The method also includes forming a warpage control dielectric layer over the redistribution pad. The method also includes forming a bond via and a bond pad over the redistribution pad, the bond pad being in the warpage control dielectric layer, the bond via being electrically coupled to the redistribution pad.

公开(公告)号：US20250105090A1

公开(公告)日：2025-03-27

申请号：US18974937

申请日：2024-12-10

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chien-Chia Chiu ,  Li-Han Hsu

IPC: H01L23/40 ,  H01L23/04 ,  H01L23/10 ,  H01L23/16 ,  H01L23/31

Abstract: A semiconductor device including a circuit substrate, a chip package, and a stiffener ring is provided. The chip package is disposed on and electrically connected to the circuit substrate, the chip package includes a pair of first parallel sides and a pair of second parallel sides shorter than the pair of first parallel sides. The stiffener ring is disposed on the circuit substrate, the stiffener ring includes first stiffener portions extending along a direction substantially parallel with the pair of first parallel sides and second stiffener portions extending along the direction substantially parallel with the pair of second parallel sides. The first stiffener portions are connected to the second stiffener portions, and the second stiffener portions is mechanically weaker than the first stiffener portions. A semiconductor device including stiffener lids is also provided.

公开(公告)号：US20250102916A1

公开(公告)日：2025-03-27

申请号：US18973300

申请日：2024-12-09

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Liang-Yi Chang ,  Tai-Chun Huang ,  Chi On Chui

IPC: G03F7/09 ,  G03F7/16 ,  G03F7/20 ,  G03F7/26 ,  H01L21/027 ,  H01L21/3105 ,  H01L21/311

Abstract: Multi-layer photoresists, methods of forming the same, and methods of patterning a target layer using the same are disclosed. In an embodiment, a method includes depositing a reflective film stack over a target layer, the reflective film stack including alternating layers of a first material and a second material, the first material having a higher refractive index than the second material; depositing a photosensitive layer over the reflective film stack; patterning the photosensitive layer to form a first opening exposing the reflective film stack, patterning the photosensitive layer including exposing the photosensitive layer to a patterned energy source, the reflective film stack reflecting at least a portion of the patterned energy source to a backside of the photosensitive layer; patterning the reflective film stack through the first opening to form a second opening exposing the target layer; and patterning the target layer through the second opening.