中科微点-全球专利检索

  1. Login
  2. Sign Up

Search Results

83 records (took 0.025 seconds)

    Method for manufacturing a micro-electro-mechanical structure
    75.
    发明授权
    Method for manufacturing a micro-electro-mechanical structure 失效
    微电子机械结构的制造方法

    公开(公告)号：US07524767B2

    公开(公告)日：2009-04-28

    申请号：US11239259

    申请日：2005-09-29

    Applicant: Dan W. Chilcott

    Inventor： Dan W. Chilcott

    IPC: H01L21/302

    CPC classification number: B81C1/00531 ,  B81B2203/033 ,  B81C2201/0132 ,  B81C2201/0142

    Abstract: A technique for manufacturing a micro-electro-mechanical (MEM) structure includes a number of steps. Initially, a substrate is provided. Next, a plurality of trenches are etched into the substrate with a first etch. Then, a charging layer is formed at a bottom of each of the trenches to form undercut trenches. Finally, a second etch is provided into the undercut trenches. The charging layer causes the second etch to laterally etch foots in the substrate between the undercut trenches. The footers undercut the substrate to release a portion of the substrate for providing a movable structure between the undercut trenches and above the footers.

    Abstract translation: 微机电（MEM）结构的制造技术包括多个步骤。 首先，提供基板。 接下来，通过第一蚀刻将多个沟槽蚀刻到衬底中。 然后，在每个沟槽的底部形成充电层以形成底切沟槽。 最后，在底切沟槽中提供第二蚀刻。 充电层导致第二蚀刻在底切沟槽之间横向蚀刻衬底中的脚。 脚底底切基板以释放基板的一部分，以在底切沟槽和页脚之上提供可移动结构。

    Method and system for xenon fluoride etching with enhanced efficiency
    77.
    发明申请
    Method and system for xenon fluoride etching with enhanced efficiency 审中-公开
    氙氟化物蚀刻方法和系统提高了效率

    公开(公告)号：US20060065622A1

    公开(公告)日：2006-03-30

    申请号：US11083030

    申请日：2005-03-17

    Applicant: Philip Floyd ,  William Cummings

    Inventor： Philip Floyd ,  William Cummings

    IPC: C23F1/00 ,  C03C25/68 ,  B44C1/22 ,  H01L21/306

    CPC classification number: H01L21/3065 ,  B81B2201/047 ,  B81C1/00531 ,  B81C2201/0142 ,  B81C2201/056 ,  G02B26/001 ,  H01L21/32135 ,  H01L21/67069

    Abstract: Provided herein is an apparatus and a method useful for manufacturing MEMS devices. An aspect of the disclosed apparatus provides a substrate comprising an etchable material exposed to a solid-state etchant, wherein the substrate and the solid-state etchant are disposed in an etching chamber. In some embodiments, the solid state etchant is moved into close proximity to the substrate. In other embodiments, a configurable partition is between the substrate and the solid-state etchant is opened. The solid-state etchant forms a gas-phase etchant suitable for etching the etchable material. In some preferred embodiments, the solid-state etchant is solid xenon difluoride. The apparatus and method are advantageously used in performing a release etch in the fabrication of optical modulators.

    Abstract translation: 本文提供了一种用于制造MEMS装置的装置和方法。 所公开的装置的一个方面提供了一种包括暴露于固态蚀刻剂的可蚀刻材料的衬底，其中衬底和固态蚀刻剂设置在蚀刻室中。 在一些实施例中，固态蚀刻剂移动到靠近基板的位置。 在其它实施例中，可配置的分隔件在基板之间并且打开固态蚀刻剂。 固态蚀刻剂形成适于蚀刻可蚀刻材料的气相蚀刻剂。 在一些优选的实施方案中，固态蚀刻剂是固体氙二氟化物。 该装置和方法有利地用于在光学调制器的制造中执行释放蚀刻。

    Composite dielectric with improved etch selectivity for high voltage MEMS structures
    78.
    发明授权
    Composite dielectric with improved etch selectivity for high voltage MEMS structures 有权
    具有改进的高电压MEMS结构的蚀刻选择性的复合电介质

    公开(公告)号：US06747338B1

    公开(公告)日：2004-06-08

    申请号：US10306639

    申请日：2002-11-27

    Applicant: Thomas K. Nunan ,  David E. Grosjean ,  Denis M. O'Kane ,  James S. Sellars

    Inventor： Thomas K. Nunan ,  David E. Grosjean ,  Denis M. O'Kane ,  James S. Sellars

    IPC: H01L2358

    CPC classification number: B81C1/00595 ,  B81C1/00698 ,  B81C2201/0109 ,  B81C2201/0142 ,  B81C2201/016 ,  B81C2201/019

    Abstract: A method of manufacturing MEMS structures and devices that allows the fabrication of dielectric structures with improved etch selectivity and good electrical leakage characteristics. The dielectric structure includes a composite stack of silicon nitride sub-layers with a silicon-rich nitride sub-layer and a stoichiometric silicon nitride sub-layer at opposite ends of the stack. Alternatively, the dielectric structure includes a single silicon nitride layer providing a graded change in silicon content through the dielectric layer, from silicon-rich nitride to stoichiometric silicon nitride.

    Abstract translation: 制造MEMS结构和器件的方法，其允许制造具有改进的蚀刻选择性和良好漏电特性的电介质结构。 电介质结构包括在堆叠的相对端处具有富硅氮化物子层和化学计量氮化硅子层的氮化硅子层的复合叠层。 或者，电介质结构包括单个氮化硅层，其通过介电层提供硅含量的梯度变化，从富含硅的氮化物到化学计量的氮化硅。

    COMPOSITE DIELECTRIC WITH IMPROVED ETCH SELECTIVITY FOR HIGH VOLTAGE MEMS STRUCTURES
    79.
    发明申请
    COMPOSITE DIELECTRIC WITH IMPROVED ETCH SELECTIVITY FOR HIGH VOLTAGE MEMS STRUCTURES 有权
    具有改进的高电压MEMS结构的蚀刻选择性的复合电介质

    公开(公告)号：US20040099928A1

    公开(公告)日：2004-05-27

    申请号：US10306639

    申请日：2002-11-27

    Inventor： Thomas K. Nunan ,  David E. Grosjean ,  Denis M. O'Kane ,  James S. Sellars

    IPC: H01L021/76

    CPC classification number: B81C1/00595 ,  B81C1/00698 ,  B81C2201/0109 ,  B81C2201/0142 ,  B81C2201/016 ,  B81C2201/019

    Abstract: A method of manufacturing MEMS structures and devices that allows the fabrication of dielectric structures with improved etch selectivity and good electrical leakage characteristics. The dielectric structure includes a composite stack of silicon nitride sub-layers with a silicon-rich nitride sub-layer and a stoichiometric silicon nitride sub-layer at opposite ends of the stack. Alternatively, the dielectric structure includes a single silicon nitride layer providing a graded change in silicon content through the dielectric layer, from silicon-rich nitride to stoichiometric silicon nitride.

    Abstract translation: 制造MEMS结构和器件的方法，其允许制造具有改进的蚀刻选择性和良好漏电特性的电介质结构。 电介质结构包括在堆叠的相对端处具有富硅氮化物子层和化学计量氮化硅子层的氮化硅子层的复合叠层。 或者，电介质结构包括单个氮化硅层，其通过介电层提供硅含量的梯度变化，从富含硅的氮化物到化学计量的氮化硅。

    Method for anisotropic plasma etching of semiconductors
    80.
    发明授权
    Method for anisotropic plasma etching of semiconductors 有权
    半导体各向异性等离子体蚀刻方法

    公开(公告)号：US06720268B1

    公开(公告)日：2004-04-13

    申请号：US09720758

    申请日：2000-12-28

    Applicant: Franz Laermer ,  Andrea Schilp

    Inventor： Franz Laermer ,  Andrea Schilp

    IPC: H01L21311

    CPC classification number: B81C1/00626 ,  B81C99/0065 ,  B81C2201/0132 ,  B81C2201/0142 ,  H01L21/3065 ,  H01L21/30655

    Abstract: A method of anisotropic etching of structures in a semiconductor body, in particular of recesses in a silicon body (18) exactly defined laterally by an etching mask, by using a plasma (28) is proposed. An ion acceleration voltage induced in particular by a high-frequency AC voltage is applied to the semiconductor body at least during an etching step having a predefined duration. The duration of the etching step is further subdivided into at least two etching segments between which the ion acceleration voltage applied is modified each time. Preferably two etching segments are provided, a higher acceleration voltage being used during the first etching segment than during the second etching step. The length of the first etching segment can furthermore be determined dynamically or statically during the etching steps using a device for the detection of a polymer breakdown. In order to generate and adjust the value of the acceleration voltage, preferably high-frequency pulses or pulse packets having an adjustable pulse/pause ratio are used.

    Abstract translation: 提出了通过使用等离子体（28）在半导体本体中特别是通过蚀刻掩模横向确定的硅体（18）中的凹部的各向异性蚀刻方法。 至少在具有预定持续时间的蚀刻步骤期间，将特别由高频AC电压引起的离子加速电压施加到半导体本体。 蚀刻步骤的持续时间进一步细分为至少两个蚀刻段，每个蚀刻段之间每次修改施加的离子加速电压。 优选地，提供两个蚀刻段，在第一蚀刻段期间比在第二蚀刻步骤期间使用更高的加速电压。 此外，可以在使用用于检测聚合物击穿的装置的蚀刻步骤期间动态地或静态地确定第一蚀刻段的长度。 为了产生和调整加速电压的值，优选使用具有可调脉冲/暂停比的高频脉冲或脉冲数据包。

Patent Agency Ranking