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111 条记录 (耗时 0.02 秒)

    Semiconductor element
    71.
    发明授权
    Semiconductor element 有权
    半导体元件

    公开(公告)号：US06781164B2

    公开(公告)日：2004-08-24

    申请号：US10690290

    申请日：2003-10-21

    申请人： Yuji Hori ,  Tomohiko Shibata ,  Osamu Oda ,  Mitsuhiro Tanaka

    发明人： Yuji Hori ,  Tomohiko Shibata ,  Osamu Oda ,  Mitsuhiro Tanaka

    IPC分类号： H01L31072

    CPC分类号： H01L29/66318 ,  H01L21/0237 ,  H01L21/0242 ,  H01L21/02458 ,  H01L21/0254 ,  H01L21/0262 ,  H01L29/2003 ,  H01L29/66462 ,  H01L29/66856

    摘要： An AlN film as an underlayer is epitaxially grown on a substrate having a dislocation density of 1011/cm2 or below and a crystallinity of 90 seconds or below in full width at half maximum (FWHM) of an X-ray rocking curve at (002) reflection. Then, on the AlN film an n-GaN film is epitaxially grown as a conductive layer having a dislocation density of 1010/cm2 or below and a crystallinity of 150 seconds or below in full width at half maximum (FWHM) of an X-ray rocking curve at (002) reflection, to fabricate a semiconductor element.

    摘要翻译： 将作为底层的AlN膜外延生长在具有10 11 / cm 2以下的位错密度和90秒以下的结晶度的X射线的半峰全宽（FWHM）的基板上 （002）反射的摇摆曲线。 然后，在AlN膜上，将n-GaN膜外延生长为位错密度为10 10 / cm 2以下的导电层，在半高宽度下为150秒以下的结晶度（FWHM ）（002）反射的X射线摇摆曲线，以制造半导体元件。

    Methods of fabricating silicon carbide metal-semiconductor field effect transistors
    72.
    发明申请
    Methods of fabricating silicon carbide metal-semiconductor field effect transistors 有权
    制造碳化硅金属半导体场效应晶体管的方法

    公开(公告)号：US20040159865A1

    公开(公告)日：2004-08-19

    申请号：US10706641

    申请日：2003-11-12

    发明人： Scott T. Allen ,  John W. Palmour ,  Terrence S. Alcorn

    IPC分类号： H01L029/06

    CPC分类号： H01L29/8128 ,  H01L21/7605 ,  H01L29/1608 ,  H01L29/47 ,  H01L29/66068 ,  H01L29/66856 ,  H01L29/812

    摘要： SiC MESFETs are disclosed which utilize a semi-insulating SiC substrate which substantially free of deep-level dopants. Utilization of the semi-insulating substrate may reduce back-gating effects in the MESFETs. Also provided are SiC MESFETs with a two recess gate structure. MESFETS with a selectively doped p-type buffer layer are also provided. Utilization of such a buffer layer may reduce output conductance by a factor of 3 and produce a 3 db increase in power gain over SiC MESFETs with conventional p-type buffer layers. A ground contact may also be provided to the p-type buffer layer and the p-type buffer layer may be made of two p-type layers with the layer formed on the substrate having a higher dopant concentration. SiC MESFETs according to embodiments of the present invention may also utilize chromium as a Schottky gate material. Furthermore, an oxide-nitride-oxide (ONO) passivation layer may be utilized to reduce surface effects in SiC MESFETs. Also, source and drain ohmic contacts may be formed directly on the n-type channel layer, thus, the nnull regions need not be fabricated and the steps associated with such fabrication may be eliminated from the fabrication process. Methods of fabricating such SiC MESFETs and gate structures for SiC FETs as well as passivation layers are also disclosed.

    摘要翻译： 公开了利用基本上不含深层掺杂剂的半绝缘SiC衬底的SiC MESFET。 半绝缘衬底的利用可能会降低MESFET的反向栅极效应。 还提供了具有两个凹陷栅极结构的SiC MESFET。 还提供了具有选择性掺杂的p型缓冲层的MESFET。 使用这种缓冲层可以将输出电导降低3倍，并且与传统的p型缓冲层相比，产生比SiC MESFET增加3db的功率增益。 还可以向p型缓冲层提供接地触点，并且p型缓冲层可以由两层p型层制成，其中在衬底上形成的层具有较高的掺杂剂浓度。 根据本发明实施例的SiC MESFET也可以使用铬作为肖特基栅极材料。 此外，可以利用氧化物 - 氮化物 - 氧化物（ONO）钝化层来降低SiC MESFET中的表面效应。 此外，源极和漏极欧姆接触可以直接形成在n型沟道层上，因此，不需要制造n +区，并且可以从制造过程中消除与这种制造相关联的步骤。 还公开了制造这种SiC MESFET和用于SiC FET以及钝化层的栅极结构的方法。

    TRANSISTORS HAVING BURIED P-TYPE LAYERS BENEATH THE SOURCE REGION
    74.
    发明申请
    TRANSISTORS HAVING BURIED P-TYPE LAYERS BENEATH THE SOURCE REGION 有权
    带有P型层的晶体管源自于源区

    公开(公告)号：US20040099888A1

    公开(公告)日：2004-05-27

    申请号：US10304272

    申请日：2002-11-26

    发明人： Saptharishi Sriram

    IPC分类号： H01L029/76

    CPC分类号： H01L29/66856 ,  H01L29/1608 ,  H01L29/2003 ,  H01L29/66068 ,  H01L29/812 ,  H01L29/8128

    摘要： The present invention provides a unit cell of a metal-semiconductor field-effect transistor (MESFET). The unit cell of the MESFET includes a source, a drain and a gate. The gate is disposed between the source and the drain and on an n-type conductivity channel layer. A p-type conductivity region is provided beneath the source and has an end that extends towards the drain. The p-type conductivity region is spaced apart from the n-type conductivity channel region and is electrically coupled to the source.

    摘要翻译： 本发明提供了一种金属半导体场效应晶体管（MESFET）的单元。 MESFET的单元包括源极，漏极和栅极。 栅极设置在源极和漏极之间以及n型导电沟道层上。 在源极下方提供p型导电区域，并且具有朝向漏极延伸的端部。 p型导电区域与n型导电沟道区域间隔开并且电耦合到源极。

    Structures and methods for composite semiconductor field effect transistors
    77.
    发明申请
    Structures and methods for composite semiconductor field effect transistors 审中-公开
    复合半导体场效应晶体管的结构和方法

    公开(公告)号：US20030020103A1

    公开(公告)日：2003-01-30

    申请号：US09911448

    申请日：2001-07-25

    申请人： MOTOROLA, INC.

    发明人： Edgar H. Callaway JR. ,  Robert E. Stengel ,  David E. Bockelman

    IPC分类号： H01L029/74 ,  H01L031/112 ,  H01L021/84

    CPC分类号： H01L29/66856 ,  H01L21/8258 ,  H01L27/0605 ,  H01L29/812

    摘要： A composite semiconductor including silicon and compound semiconductor, and having a metal semiconductor field effect transistor (MESFET) integrated at least partially with the silicon and at least partially with the GaAs having a silicon back gate is provided. The back gate for the MESFET may be formed by doping a region of the monocrystalline silicon substrate before forming the transistor. In a structure according the invention, integrated circuits may be provided to match the threshold voltages of one MESFET to another, improve the transconductance of a MESFET, and improve the switching speed of a MESFET.

    摘要翻译： 提供了包括硅和化合物半导体的复合半导体，并且具有至少部分地与硅并且至少部分地与具有硅背栅的GaAs集成的金属半导体场效应晶体管（MESFET）。 用于MESFET的背栅可以通过在形成晶体管之前掺杂单晶硅衬底的区域来形成。 在根据本发明的结构中，可以提供集成电路以将一个MESFET的阈值电压与另一个MESFET的阈值电压相匹配，改善MESFET的跨导，并提高MESFET的开关速度。

    Semiconductor element
    78.
    发明申请
    Semiconductor element 有权
    半导体元件

    公开(公告)号：US20020113249A1

    公开(公告)日：2002-08-22

    申请号：US10007099

    申请日：2001-12-04

    申请人： NGK Insulators, Ltd.

    发明人： Yuji Hori ,  Tomohiko Shibata ,  Osamu Oda ,  Mitsuhiro Tanaka

    IPC分类号： H01L031/0328

    CPC分类号： H01L29/66318 ,  H01L21/0237 ,  H01L21/0242 ,  H01L21/02458 ,  H01L21/0254 ,  H01L21/0262 ,  H01L29/2003 ,  H01L29/66462 ,  H01L29/66856

    摘要： On a substrate is epitaxially grown an AlN film as an underlayer having a dislocation density of 1011/cm2 or below and a crystallinity of 90 seconds or below in full width at half maximum (FWHM) of X-ray rocking curve at (002) reflection. Then, on the AlN film is epitaxially grown an n-GaN film as a conductive layer having a dislocation density of 1010/cm2 or below and a crystallinity of 150 seconds or below in full width at half maximum (FWHM) of X-ray rocking curve at (002) reflection, to fabricate a semiconductor element.

    摘要翻译： 在（002）反射的X射线摇摆曲线的半峰全宽（FWHM）下，在基板上外延生长具有位错密度为1011 / cm 2以下且90秒以下的结晶度的AlN膜作为底层 。 然后，在AlN膜上外延生长具有位移密度为1010 / cm 2以下的导电层的n-GaN膜，X射线摇摆的半高宽度（FWHM）为150秒以下的结晶度 （002）反射的曲线，以制造半导体元件。

    Manufacturable GaAs VFET process
    79.
    发明授权
    Manufacturable GaAs VFET process 失效
    可制造的GaAs VFET工艺

    公开(公告)号：US06309918B1

    公开(公告)日：2001-10-30

    申请号：US09157430

    申请日：1998-09-21

    申请人： Jenn-Hwa Huang ,  Benjamin W. Gable ,  Kurt Eisenbeiser ,  David Rhine

    发明人： Jenn-Hwa Huang ,  Benjamin W. Gable ,  Kurt Eisenbeiser ,  David Rhine

    IPC分类号： H01L21338

    CPC分类号： H01L29/66856 ,  H01L29/8122 ,  Y10S438/945

    摘要： A manufacturable GaAs VFET process includes providing a doped GaAs substrate with a lightly doped first epitaxial layer thereon and a heavily doped second epitaxial layer positioned on the first epitaxial layer. A temperature tolerant conductive layer is positioned on the second epitaxial layer and patterned to define a plurality of elongated, spaced apart source areas. Using the patterned conductive layer, a plurality of gate trenches are etched into the first epitaxial layer adjacent the source areas. The bottoms of the gate trenches are implanted and activated to form gate areas. A gate contact is deposited in communication with the implanted gate areas, a source contact is deposited in communication with the patterned conductive layer overlying the source areas, and a drain contact is deposited on the rear surface of the substrate.

    摘要翻译： 可制造的GaAs VFET工艺包括在其上提供掺杂的GaAs衬底和其上的轻掺杂的第一外延层和位于第一外延层上的重掺杂的第二外延层。 耐温导电层定位在第二外延层上并且被图案化以限定多个细长的间隔开的源极区域。 使用图案化的导电层，多个栅极沟槽被蚀刻到与源极区域相邻的第一外延层中。 栅极沟槽的底部被植入和激活以形成栅极区域。 栅极接触被沉积成与植入的栅极区域连通，源极接触层沉积成与覆盖在源极区域上的图案化导电层连通，并且漏极接触沉积在衬底的后表面上。