公开(公告)号：US20230083088A1

公开(公告)日：2023-03-16

申请号：US18050779

申请日：2022-10-28

申请人： TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.

发明人： Shih-Lien Linus LU ,  Bo-Feng YOUNG ,  Han-Jong CHIA ,  Yu-Ming LIN ,  Sai-Hooi YEONG

IPC分类号： G11C11/4094 ,  G11C5/02 ,  G11C11/4074 ,  G11C11/4099 ,  G11C11/408

摘要： A method of writing data to a memory array of three-terminal memory cells includes simultaneously programming a first subset of memory cells in a first column of the memory array to a first logic level by activating a first select line of the first column and a first bit line of the first column, and simultaneously programming a second subset of memory cells in the first column to the first logic level by activating the first select line and a second bit line of the first column.

公开(公告)号：US11600326B2

公开(公告)日：2023-03-07

申请号：US17154945

申请日：2021-01-21

申请人： MICRON TECHNOLOGY, INC.

发明人： John Schreck ,  Dan Penney

IPC分类号： G11C15/04 ,  G11C11/406 ,  G11C11/4094 ,  G11C11/408 ,  G11C11/4096 ,  G11C11/4074 ,  G11C11/419 ,  G11C16/28

摘要： Embodiments of the disclosure are drawn to apparatuses and methods for content addressable memory (CAM) cells. Each CAM cell may include a comparator portion which stores a bit of information. Each CAM cell may also include a comparator portion, which compares an external bit to the stored bit. A group of CAM cells may be organized into a CAM register, with each CAM cell coupled in common to a signal line. Any of the CAM cells may change a voltage on the signal line if the external bit does not match the stored bit.

公开(公告)号：US11600317B2

公开(公告)日：2023-03-07

申请号：US17332414

申请日：2021-05-27

申请人： Taiwan Semiconductor Manufacturing Company, Ltd.

发明人： Shigeki Shimomura ,  Jonathan Tsung-Yung Chang

IPC分类号： G11C11/4074 ,  G11C11/4094 ,  H03K19/017 ,  G11C5/06 ,  G11C11/408

摘要： A memory device is provided. The memory device includes a bit cell having a first invertor connected between a first node and a second node and a second invertor connected between the first node and the second node. The first invertor and the second invertor are cross coupled at a first data node and a second data node. The memory device further includes a pull down circuit connected to the second node. The pull down circuit is operative to pull down a voltage of the second node below a ground voltage in response to an enable signal.

公开(公告)号：US11599475B2

公开(公告)日：2023-03-07

申请号：US17222642

申请日：2021-04-05

申请人： Micron Technology, Inc.

发明人： Richard C. Murphy

IPC分类号： G06F12/0864 ,  G06F12/0811 ,  G06F9/30 ,  G11C7/10 ,  G11C11/4091 ,  G11C11/4096 ,  G06F12/0895 ,  G06F12/084 ,  G11C11/4094 ,  G11C19/00

摘要： An example includes a compute component, a memory and a controller coupled to the memory. The controller configured to operate on a block select and a subrow select as metadata to a cache line to control placement of the cache line in the memory to allow for a compute enabled cache.

公开(公告)号：US11587610B2

公开(公告)日：2023-02-21

申请号：US17333638

申请日：2021-05-28

申请人： Microsoft Technology Licensing, LLC

发明人： Pramod Kolar ,  Stephen Edward Liles

IPC分类号： G11C7/10 ,  G11C11/4096 ,  G11C11/408 ,  G11C5/06 ,  G11C11/4094 ,  G11C11/4091

摘要： Memory systems having flying bitlines for improved burst mode read operations and related methods are provided. A memory system comprises a memory array including a first set of memory cells coupled to a first inner wordline and a second set of memory cells coupled to a first outer wordline. The memory system includes a control unit configured to generate control signals for simultaneously: asserting a first wordline signal on the first inner wordline coupled to each of a plurality of inner bitlines, and asserting a second wordline signal on the first outer wordline coupled to each of a plurality of outer bitlines, where each of the plurality of outer bitlines includes a first portion configured to fly over or fly under a corresponding inner bitline, and outputting data from each of the first set of memory cells and the second set of memory cells as part of a burst.

公开(公告)号：US20230050097A1

公开(公告)日：2023-02-16

申请号：US17659337

申请日：2022-04-15

申请人： CHANGXIN MEMORY TECHNOLOGIES, INC.

发明人： Peihuan WANG

IPC分类号： G06F30/398 ,  G06F30/392 ,  G11C11/408 ,  G11C11/4094

摘要： Embodiments of the present application provide a memory array circuit, a memory array layout and a verification method. The memory array circuit includes: M word lines (WLs); M WL break nodes, each being configured to separate a corresponding one of the WLs into a first WL pin and a second WL pin; N bit lines (BLs); and N BL break nodes, each being configured to separate a corresponding one of the BLs into a first BL pin and a second BL pin, wherein the M and the N each are a positive even number.

公开(公告)号：US20230031904A1

公开(公告)日：2023-02-02

申请号：US17388678

申请日：2021-07-29

申请人： Micron Technology, Inc.

发明人： Eric S. Carman ,  Durai Vishak Nirmal Ramaswamy ,  Richard E Fackenthal ,  Kamal M. Karda ,  Karthik Sarpatwari ,  Haitao Liu ,  Duane R. Mills ,  Christian Caillat

IPC分类号： H01L27/108 ,  H01L29/24 ,  G11C11/4074 ,  G11C11/408 ,  G11C11/4094 ,  G11C11/4096

摘要： Some embodiments include apparatuses and methods of operating such apparatuses. One of such apparatuses includes a data line, a conductive region, and a memory cell including a first transistor and a second transistor. The first transistor includes a first channel region coupled to the data line and the conductive region, a charge storage structure, and a first gate. The second transistor includes a second channel region coupled to the data line and the charge storage structure, and a second gate. The first gate is electrically separated from the second gate and opposite from the second gate in a direction from the first channel region to the second channel region.

公开(公告)号：US20230030801A1

公开(公告)日：2023-02-02

申请号：US17965527

申请日：2022-10-13

申请人： YANGTZE MEMORY TECHNOLOGIES CO., LTD.

发明人： Jianquan Jia ,  Ying Cui ,  Kaikai You

IPC分类号： G11C11/408 ,  G11C11/4074 ,  G11C11/4094 ,  G11C11/4099 ,  G11C11/419

摘要： A non-volatile memory device includes a plurality of word lines and a control circuit. The control circuit is configured to apply a first word line pre-pulse signal of a plurality of word line pre-pulse signals to a first group of the plurality of word lines, apply a second word line pre-pulse signal of the plurality of word line pre-pulse signals to a second group of the plurality of word lines during a pre-charge period, and apply a third word line pre-pulse signal of the plurality of word lines pre-pulse signals to a third group of the plurality of word lines during the pre-charge period. A voltage level of the second word line pre-pulse signal is greater than that of the first word line pre-pulse signal, and a voltage level of the third word line pre-pulse signal is greater than that of the second word line pre-pulse signal.

公开(公告)号：US11568902B2

公开(公告)日：2023-01-31

申请号：US16882064

申请日：2020-05-22

申请人： SEMICONDUCTOR ENERGY LABORATORY CO., LTD.

发明人： Jun Koyama ,  Shunpei Yamazaki

IPC分类号： G11C11/24 ,  G11C5/10 ,  G11C7/12 ,  G11C11/408 ,  G11C11/4094 ,  G11C11/4097 ,  H01L27/02 ,  H01L27/06 ,  H01L27/108 ,  H01L27/12 ,  H01L29/786 ,  G11C7/18

摘要： An object of one embodiment of the present invention is to propose a memory device in which a period in which data is held is ensured and memory capacity per unit area can be increased. In the memory device of one embodiment of the present invention, bit lines are divided into groups, and word lines are also divided into groups. The word lines assigned to one group are connected to the memory cell connected to the bit lines assigned to the one group. Further, the driving of each group of bit lines is controlled by a dedicated bit line driver circuit of a plurality of bit line driver circuits. In addition, cell arrays are formed on a driver circuit including the above plurality of bit line driver circuits and a word line driver circuit. The driver circuit and the cell arrays overlap each other.

公开(公告)号：US20230011345A1

公开(公告)日：2023-01-12

申请号：US17369873

申请日：2021-07-07

申请人： Micron Technology, Inc.

发明人： Eric Carman ,  Daniele Vimercati

IPC分类号： G11C11/4091 ,  G11C11/4074 ,  G11C11/4096 ,  G11C11/4094 ,  G11C11/4099 ,  G11C7/06

摘要： Methods, systems, and devices for sense amplifier with digit line multiplexing are described. A method includes precharging an input and an output of an amplifier stage of a sense component to a first voltage based on a read operation associated with a memory cell. The method includes precharging a first side and a second side of a latch stage of the sense component to the first voltage based on precharging the output of the amplifier stage to the first voltage, the latch stage coupled with the amplifier stage. The method may also include coupling a second voltage from a digit line associated with the memory cell to the input of the amplifier stage, the amplifier stage generating a third voltage on the output based on coupling the second voltage to the input, and the latch stage latching a logic value associated with the memory cell based on the third voltage.