公开(公告)号：US09231014B2

公开(公告)日：2016-01-05

申请号：US14464793

申请日：2014-08-21

Applicant: STMicroelectronics SA ,  Commissariat A L'Energie Atomique et aux Energies Alternatives

Inventor： Laurent Frey ,  Michel Marty

IPC: H01L29/06 ,  H01L27/14 ,  H01L31/062 ,  H01L21/00 ,  H01L27/146 ,  H01L31/0232 ,  H01L31/107 ,  H01L31/0352

CPC classification number: H01L27/14685 ,  H01L27/14621 ,  H01L27/14625 ,  H01L27/14627 ,  H01L27/1464 ,  H01L27/14643 ,  H01L31/02327 ,  H01L31/035236 ,  H01L31/107

Abstract: A back side illumination photodiode includes a light-receiving back side surface of a semiconductor material substrate. An area of the light-receiving back side surface includes a recess. The recess is filled with a material having an optical index that is lower than an optical index of the semiconductor material substrate. Both the substrate and the filling material are transparent to an operating wavelength of the photodiode. The recess may be formed to have a ring shape.

Abstract translation: 背面照明光电二极管包括半导体材料基板的受光背面。 光接收侧面的面积包括凹部。 凹部填充有光学折射率低于半导体材料基板的光学折射率的材料。 衬底和填充材料都对于光电二极管的工作波长是透明的。 凹部可以形成为环形。

公开(公告)号：US20150372388A1

公开(公告)日：2015-12-24

申请号：US14726866

申请日：2015-06-01

Applicant: STMICROELECTRONICS SA

Inventor： Baudouin MARTINEAU ,  Olivier RICHARD ,  Didier BELOT ,  Pierre DAUTRICHE

IPC: H01Q13/06

CPC classification number: H01Q13/06 ,  H01P3/16 ,  Y10T29/49018 ,  Y10T29/4902

Abstract: A connector for a plastic waveguide includes a connector body having first and second openings aligned with one another. The first opening is configured to receive the plastic waveguide. A radio frequency (RF) antenna is positioned within the second opening of the connector body.

Abstract translation: 用于塑料波导的连接器包括具有彼此对准的第一和第二开口的连接器主体。 第一开口被配置为接收塑料波导。 射频（RF）天线定位在连接器主体的第二开口内。

公开(公告)号：US20150364209A1

公开(公告)日：2015-12-17

申请号：US14832802

申请日：2015-08-21

Applicant: STMicroelectronics SA

Inventor： Philippe Candelier ,  Joel Damiens ,  Elise Le Roux

IPC: G11C17/16 ,  H01L27/112 ,  G11C17/18

CPC classification number: G11C17/165 ,  G11C17/18 ,  H01L27/101 ,  H01L27/11206

Abstract: A method for controlling the breakdown of an antifuse memory cell formed on a semiconductor substrate, including the steps of: applying a programming voltage; detecting a breakdown time; and interrupting the application of the programming voltage at a time following the breakdown time by a post-breakdown time.

Abstract translation: 一种用于控制形成在半导体衬底上的反熔层存储单元击穿的方法，包括以下步骤：施加编程电压; 检测故障时间; 并且在故障时间之后的故障时间之后中断施加编程电压。

公开(公告)号：US20150338687A1

公开(公告)日：2015-11-26

申请号：US14638345

申请日：2015-03-04

Applicant: STMICROELECTRONICS SA

Inventor： Jean-Robert MANOUVRIER

IPC: G02F1/025

CPC classification number: G02F1/025 ,  G02F1/0123 ,  G02F1/225 ,  G02F1/2255

Abstract: A semiconductor electro-optical phase shifter may include a substrate, an optical waveguide segment (12) formed on the substrate, and first and second zones of opposite conductivity types configured to form a first bipolar junction perpendicular to the substrate. The phase shifter may also include a dynamic control structure configured to reverse bias the first junction and a static control structure configured to direct a quiescent current in the second zone, parallel to the first junction.

Abstract translation: 半导体电光移相器可以包括衬底，形成在衬底上的光波导段（12）以及被配置为形成垂直于衬底的第一双极结的相反导电类型的第一和第二区。 移相器还可以包括被配置为反向偏置第一结的动态控制结构和被配置成引导平行于第一结的第二区中的静态电流的静态控制结构。

公开(公告)号：US09165908B2

公开(公告)日：2015-10-20

申请号：US13932134

申请日：2013-07-01

Applicant: Commissariat à l'énergie atomique et aux énergies alternatives ,  STMicroelectronics SA

Inventor： Claire Fenouillet-Beranger ,  Pascal Fonteneau

IPC: H01L21/70 ,  H01L25/07 ,  H01L27/02 ,  H01L27/12

CPC classification number: H01L25/07 ,  H01L27/0262 ,  H01L27/1207 ,  H01L2924/0002 ,  H01L2924/00

Abstract: An integrated circuit includes four electronic components, a buried UTBOX layer under and plumb with the electronic components, and two pairs of oppositely doped ground planes plumb with corresponding components under the layer. A first isolation trench mutually isolates the ground planes from corresponding wells made plumb and in contact with the ground planes and exhibiting the first doping type. Bias electrodes contact respective wells and ground planes. One pair of electrodes is for connecting to a first bias voltage and the other pair is for connecting to a second bias voltage. Also included are a semiconductor substrate exhibiting the first type of doping and a deeply buried well exhibiting the second type of doping. The deeply buried well contacts the other wells and separates them from the substrate. Finally, a control electrode couples to the deeply buried well.

Abstract translation: 集成电路包括四个电子部件，在电子部件下方并且铅垂的埋入的UTBOX层和在层下方具有相应部件的两对相对掺杂的接地平面。 第一隔离沟槽将接地层与相应的铅垂阱相分离并与接地层接触并呈现出第一掺杂型。 偏置电极接触相应的阱和接地层。 一对电极用于连接到第一偏置电压，另一对电极用于连接到第二偏置电压。 还包括呈现第一类掺杂的半导体衬底和呈现第二类掺杂的深埋阱。 深埋的井与其他井接触并将其与基底分离。 最后，控制电极耦合到深埋井。

公开(公告)号：US20150286238A1

公开(公告)日：2015-10-08

申请号：US14675309

申请日：2015-03-31

Applicant: STMicroelectronics SA ,  STMicroelectronics International N.V.

Inventor： Jean-Pierre Blanc ,  Pratap Narayan Singh

IPC: G05F3/16

CPC classification number: G05F3/16 ,  G05F3/26 ,  G05F3/267 ,  G05F3/30

Abstract: A reference voltage generation circuit, including a first current source in series with a first bipolar transistor; a second current source in series with a first resistor; a third current source in series with a second bipolar transistor, the third current source being assembled as a current mirror with the first current source; a second resistor between the base of the second bipolar transistor and the junction point between the current source and the first resistor; and a fourth current source in series with a third resistor, the junction point between the fourth current source and the third resistor defining a reference voltage terminal.

Abstract translation: 参考电压产生电路，包括与第一双极晶体管串联的第一电流源; 与第一电阻器串联的第二电流源; 与第二双极晶体管串联的第三电流源，所述第三电流源被组装为具有所述第一电流源的电流镜; 第二电阻器，位于第二双极晶体管的基极与电流源与第一电阻之间的连接点之间; 以及与第三电阻器串联的第四电流源，所述第四电流源和所述第三电阻器之间的连接点限定参考电压端子。

公开(公告)号：US20150253523A1

公开(公告)日：2015-09-10

申请号：US14637559

申请日：2015-03-04

Applicant: STMICROELECTRONICS SA ,  STMICROELECTRONICS (CROLLES 2) SAS

Inventor： Jean-Robert MANOUVRIER ,  Estelle Batail

IPC: G02B6/42 ,  H01L21/768 ,  H01L49/02 ,  G02B6/13

CPC classification number: G02B6/4275 ,  G02B6/13 ,  G02F1/025 ,  G02F2202/22 ,  H01L21/768 ,  H01L27/0248 ,  H01L28/40

Abstract: An ESD protection device for an electro-optical device may include an optical waveguide segment being in semiconductor material and including a central zone of a first conductivity type, and first and second wings of a second conductivity type different from the first conductivity type and being integral with the central zone. The ESD protection device may include a first conduction terminal on the first wing for defining a first protection terminal, a second conduction terminal on the second wing for defining a second protection terminal, and a resistive contact structure of the first conductivity type having a transverse arm integral with the central zone, and an end in ohmic contact with the first conduction terminal, the resistive contact structure being electrically insulated from the first wing.

Abstract translation: 用于电光装置的ESD保护装置可以包括半导体材料中的光波导段，并且包括第一导电类型的中心区，以及不同于第一导电类型的第二导电类型的第一和第二翼， 与中央区。 ESD保护装置可以包括在第一翼上的用于限定第一保护端子的第一导电端子，用于限定第二保护端子的第二机翼上的第二导电端子，以及具有横臂的第一导电类型的电阻接触结构 与中心区域成一体，并且与第一导电端子欧姆接触的端部，电阻接触结构与第一机翼电绝缘。

公开(公告)号：US09104047B2

公开(公告)日：2015-08-11

申请号：US14263068

申请日：2014-04-28

Applicant: STMICROELECTRONICS SA

Inventor： Jean-Robert Manouvrier

IPC: G02F1/01 ,  G02F1/025

CPC classification number: G02F1/025

Abstract: A semiconductor electro-optical phase shifter may include a central zone configured to be placed in an optical waveguide and doped at a first conductivity type, a first lateral zone adjacent a first face of the central region and doped at a second conductivity type, and a second lateral zone adjacent a second face of the central zone and doped at the second conductivity type.

Abstract translation: 半导体电光移相器可以包括被配置为放置在光波导中并以第一导电类型掺杂的中心区，邻近中心区的第一面并以第二导电类型掺杂的第一横向区， 第二横向区域，邻近中心区域的第二面并以第二导电类型掺杂。

公开(公告)号：US20150155170A1

公开(公告)日：2015-06-04

申请号：US14555897

申请日：2014-11-28

Applicant: COMMISSARIAT A L'ENERGIE ATOMIQUE ET AUX ENE ALT ,  STMICROELECTRONICS SA

Inventor： Shay REBOH ,  Yves MORAND ,  Hubert MORICEAU

IPC: H01L21/02 ,  H01L21/762 ,  H01L29/10 ,  H01L21/84

CPC classification number: H01L21/02689 ,  H01L21/02381 ,  H01L21/02488 ,  H01L21/02532 ,  H01L21/02667 ,  H01L21/02686 ,  H01L21/26506 ,  H01L21/7624 ,  H01L21/84 ,  H01L27/1203 ,  H01L29/1054 ,  H01L29/66742 ,  H01L29/66772 ,  H01L29/7847 ,  H01L29/78654 ,  H01L29/78684

Abstract: A method for producing a microelectronic device provided with different strained areas in the superficial layer of a semi-conductor on insulator type substrate comprising amorphizing a region of said superficial layer and then a lateral recrystallization of said region from crystalline areas adjoining this region (FIG. 1E).

Abstract translation: 一种制造在半导体绝缘体型衬底的表层中具有不同应变区域的微电子器件的方法，包括使所述表面层的区域非晶化，然后从与该区域相邻的结晶区域侧向重结晶所述区域。 1E）。

公开(公告)号：US20150137874A1

公开(公告)日：2015-05-21

申请号：US14547684

申请日：2014-11-19

Applicant: STMICROELECTRONICS SA ,  UNIVERSITY OF TWENTE

Inventor： Andreia CATHELIN ,  Bram Nauta

IPC: H03K3/012 ,  H01L21/84

CPC classification number: H03K3/012 ,  H01L21/84 ,  H01L27/1203 ,  H01L29/78603 ,  H01L29/78648

Abstract: A Silicon On Insulator current source array includes input control for receiving a control voltage, a first reference input for receiving a first reference voltage, and a second reference input for receiving a second reference voltage. A chain of several Silicon On Insulator MOS transistors, of the same type, have control electrodes all connected to the input control, first conduction electrodes are all connected to the first reference input, and second conduction electrodes are respectively connected to the second reference input through several load circuits respectively configured to be traversed by several currents when the several transistors are ON upon application of the control voltage on the input control. An input bias is coupled to a semiconductor well located below an insulating buried layer located below the chain of transistors for receiving a biasing voltage difference.

Abstract translation: 硅绝缘体电流源阵列包括用于接收控制电压的输入控制，用于接收第一参考电压的第一参考输入和用于接收第二参考电压的第二参考输入。 具有相同类型的多个绝缘体硅MOS晶体管的链条具有全部连接到输入控制的控制电极，第一导电电极全部连接到第一参考输入，第二导电电极分别连接到第二参考输入 当在输入控制上施加控制电压时，当几个晶体管导通时，多个负载电路分别被配置为被几个电流穿过。 输入偏置耦合到位于晶体管链下方的绝缘掩埋层下方的半导体阱，用于接收偏置电压差。