公开(公告)号：US20140017856A1

公开(公告)日：2014-01-16

申请号：US13933379

申请日：2013-07-02

Applicant: STMicroelectronics SA ,  Commissariat à I'ènergie atomique et aux energies alternatives

Inventor： Claire Fenouillet-Beranger ,  Pascal Fonteneau

IPC: H01L29/66

CPC classification number: H01L29/66477 ,  H01L27/0296 ,  H01L27/0688 ,  H01L27/1207

Abstract: An integrated circuit features a FET, an UTBOX layer plumb with the FET, an underlayer ground plane with first doping plumb with the FET's gate and channel, first and second underlayer semiconducting elements, both plumb with the drain or source, electrodes in contact respectively with the ground plane and with the first element, one having first doping and being connected to a first voltage, the other having the first doping and connected to a second bias voltage different from the first, a semiconducting well having the second doping and plumb with the first ground plane and both elements, a first trench isolating the first FET from other components of the integrated circuit and extending through the layer into the well, and second and third trenches isolating the FET from the electrodes, and extending to a depth less than a plane/well interface.

Abstract translation: 集成电路具有FET，具有FET的UTBOX层铅垂，具有FET的栅极和沟道的第一掺杂铅垂的下层接地层，第一和第二下层半导体元件，两者均与漏极或源极接触，电极分别接触 接地平面和第一元件，一个具有第一掺杂并且连接到第一电压，另一个具有第一掺杂并且连接到不同于第一掺杂的第二偏置电压，具有第二掺杂和铅垂的半导体阱与 第一接地平面和两个元件，第一沟槽将第一FET与集成电路的其它部件隔离并延伸穿过该阱进入阱，第二和第三沟槽将FET与电极隔离，并延伸至小于 平面/井界面。

公开(公告)号：US20140017821A1

公开(公告)日：2014-01-16

申请号：US13932134

申请日：2013-07-01

Applicant: STMicroelectronics SA ,  Commissariat a l'energie atomique et aux energies alternatives

Inventor： Claire Fenouillet-Beranger ,  Pascal Fonteneau

IPC: H01L25/07

CPC classification number: H01L25/07 ,  H01L27/0262 ,  H01L27/1207 ,  H01L2924/0002 ,  H01L2924/00

Abstract: An integrated circuit includes four electronic components, a buried UTBOX layer under and plumb with the electronic components, and two pairs of oppositely doped ground planes plumb with corresponding components under the layer. A first isolation trench mutually isolates the ground planes from corresponding wells made plumb and in contact with the ground planes and exhibiting the first doping type. Bias electrodes contact respective wells and ground planes. One pair of electrodes is for connecting to a first bias voltage and the other pair is for connecting to a second bias voltage. Also included are a semiconductor substrate exhibiting the first type of doping and a deeply buried well exhibiting the second type of doping. The deeply buried well contacts the other wells and separates them from the substrate. Finally, a control electrode couples to the deeply buried well.

Abstract translation: 集成电路包括四个电子部件，在电子部件下方并且铅垂的埋入的UTBOX层和在层下方具有相应部件的两对相对掺杂的接地平面。 第一隔离沟槽将接地层与相应的铅垂阱相分离并与接地层接触并呈现出第一掺杂型。 偏置电极接触相应的阱和接地层。 一对电极用于连接到第一偏置电压，另一对电极用于连接到第二偏置电压。 还包括呈现第一类掺杂的半导体衬底和呈现第二类掺杂的深埋阱。 深埋的井与其他井接触并将其与基底分离。 最后，控制电极耦合到深埋井。

公开(公告)号：US20130313724A1

公开(公告)日：2013-11-28

申请号：US13899326

申请日：2013-05-21

Applicant: STMicroelectronics SA

Inventor： Sylvain Joblot ,  Pierre Bar

IPC: H01L21/768 ,  H01L23/48

CPC classification number: H01L21/76898 ,  H01L21/76831 ,  H01L23/481 ,  H01L23/5222 ,  H01L23/528 ,  H01L23/53228 ,  H01L23/5329 ,  H01L23/66 ,  H01L2223/6616 ,  H01L2223/6627 ,  H01L2924/0002 ,  H01P3/003 ,  H01P3/006 ,  H01P11/003 ,  H01L2924/00

Abstract: In one embodiment there is disclosed a method for manufacturing an integrated circuit in a semiconductor substrate including through vias and a coplanar line, including the steps of: forming active components and a set of front metallization levels; simultaneously etching from the rear surface of the substrate a through via hole and a trench crossing the substrate through at least 50% of its height; coating with a conductive material the walls and the bottom of the hole and of the trench; and filling the hole and the trench with an insulating filling material; and forming a coplanar line extending on the rear surface of the substrate, in front of the trench and parallel thereto, so that the lateral conductors of the coplanar line are electrically connected to the conductive material coating the walls of the trench.

Abstract translation: 在一个实施例中，公开了一种用于在包括通孔和共面线的半导体衬底中制造集成电路的方法，包括以下步骤：形成有源部件和一组前金属化层; 同时从衬底a的后表面通过通孔和穿过衬底穿过其高度的至少50％的沟槽; 用导电材料涂覆壁和孔的底部和沟槽; 并用绝缘填充材料填充孔和沟槽; 并且在沟槽的前面并与其平行地形成在衬底的后表面上延伸的共面线，使得共面线的横向导体电连接到涂覆沟槽的壁的导电材料。

公开(公告)号：US20130262057A1

公开(公告)日：2013-10-03

申请号：US13852162

申请日：2013-03-28

Applicant: STMICROELECTRONICS SA

Inventor： Jean-Robert MANOUVRIER

IPC: G06F17/50

CPC classification number: G06F17/5036

Abstract: A model for simulating the electrical behavior of a thyristor includes a model of an NPN bipolar transistor whose emitter forms the cathode of the thyristor and the base forms a low-side control terminal of the thyristor, and a model of a PNP bipolar transistor whose emitter forms the anode of the thyristor and the base forms a high-side control terminal of the thyristor, the collector of the PNP transistor being connected to the low-side control terminal and the collector of the NPN transistor being connected to the high-side control terminal. The transistor models are present a small signal behavior over the entire range of anode currents of the thyristor, whereby the transistor models exhibit a gain drop when the anode current exits the small signal range.

Abstract translation: 用于模拟晶闸管的电气行为的模型包括其发射极形成晶闸管的阴极并且基极形成晶闸管的低侧控制端的NPN双极晶体管的模型，以及PNP双极晶体管的模型，其发射极 形成晶闸管的阳极，基极形成晶闸管的高边控制端子，PNP晶体管的集电极连接到低侧控制端子，NPN晶体管的集电极连接到高侧控制 终奌站。 晶体管模型在晶闸管的整个阳极电流范围内呈现小的信号行为，由此当阳极电流退出小信号范围时，晶体管模型呈现增益下降。

公开(公告)号：US20130105893A1

公开(公告)日：2013-05-02

申请号：US13660681

申请日：2012-10-25

Applicant: STMicroelectronics SA ,  STMicroelectronics (Crolles 2) SAS

Inventor： David Petit ,  Bruno Rauber

IPC: H01L27/088 ,  H01L21/336

CPC classification number: H01L29/7824 ,  H01L29/0696 ,  H01L29/086 ,  H01L29/1095 ,  H01L29/456 ,  H01L29/4933 ,  H01L29/665 ,  H01L29/66689

Abstract: A DMOS on SOI transistor including an elongated gate extending across the entire width of an active area; a drain region of a first conductivity type extending across the entire width of the active area; a source region of the first conductivity type extending parallel to the gate and stopping before the limit of the active area at least on one side of the transistor width, an interval existing between the limit of the source region and the limit of the active area; a bulk region of a second conductivity type extending under the gate and in said interval; a more heavily-doped region of the second conductivity type extending on a portion of said interval on the side of the limit of the active area; and an elongated source metallization extending across the entire width of the active area.

Abstract translation: SOI晶体管上的DMOS，包括延伸跨有效区域的整个宽度的细长栅极; 在有源区的整个宽度上延伸的第一导电类型的漏区; 所述第一导电类型的源极区域平行于所述栅极延伸并且在所述有源区域的极限之前至少在所述晶体管宽度的一侧上停止，所述间隔存在于所述源极区域的极限与所述有源区域的极限之间; 在栅极和所述间隔内延伸的第二导电类型的主体区域; 所述第二导电类型的更高掺杂区域在所述间隔的所述有效面积极限侧的一部分上延伸; 以及延伸穿过有效区域的整个宽度的细长源金属化。

公开(公告)号：US20040266072A1

公开(公告)日：2004-12-30

申请号：US10782724

申请日：2004-02-19

Applicant: STMICROELECTRONICS SA

Inventor： Thierry Parrassin

IPC: H01L021/26 ,  H01L021/00 ,  H01L021/337 ,  H01L021/84 ,  H01L021/42 ,  H01L021/324 ,  H01L021/477

CPC classification number: H01L23/60 ,  H01L21/76892 ,  H01L23/5256 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A buried oxide layer of an SOI substrate beneath a structure electrically isolated from the rest of a semiconductor device is made to break down so as to open a bias path for the substrate through the structure. It then suffices to connect the electrical ground of the semiconductor device to this bias path so that the ions flow away into the substrate during a focused ion beam treatment of the semiconductor device.

公开(公告)号：US20040261129A1

公开(公告)日：2004-12-23

申请号：US10765455

申请日：2004-01-27

Applicant: STMICROELECTRONICS SA

Inventor： Jean-Pierre Lagarde

IPC: H04N007/173 ,  H04N007/16

CPC classification number: H04N21/6193 ,  H04N7/17309 ,  H04N21/242 ,  H04N21/6143 ,  H04N21/8166 ,  H04N2007/17372

Abstract: A terminal for interactive telebroadcasting system comprising on the one hand a unit for adaptation to the physical telebroadcasting medium and on the other hand a control unit. The first unit comprises a receiver for receiving of a telebroadcast signal and for producing downstream information extracted from the signal, a transmission time based generator for generation of a transmission time base from the downstream information and a transmitter for transmission of a return signal, which are clocked as a function of the transmission time base. The second unit comprises a calculation unit having means of generating upstream information. The calculation unit is clocked as a function of the transmission time base.

Abstract translation: 一种用于交互式电话广播系统的终端，其一方面包括用于适应物理电话广播媒体的单元，另一方面包括控制单元。 第一单元包括用于接收电话广播信号并用于产生从信号提取的下行信息的接收机，用于从下游信息生成传输时基的基于传输时间的发生器和用于发送返回信号的发射机，它们是 作为传输时基的函数。 第二单元包括具有生成上游信息的装置的计算单元。 计算单元作为传输时基的函数计时。

公开(公告)号：US20040252704A1

公开(公告)日：2004-12-16

申请号：US10824938

申请日：2004-04-15

Applicant: STMicroelectronics SA

Inventor： Ludovic Ruat ,  Paul Kinowski ,  Alexander Czajor

IPC: H04L012/56 ,  H04L012/28 ,  H04L013/10 ,  H04L007/00

CPC classification number: G06F13/4081 ,  G06F13/385

Abstract: An asynchronous frame receiver includes an input for receiving an asynchronous frame comprising a break character, which includes a determined number of bits having a same value. A hot-plugging circuit for connecting to an asynchronous data bus that is operating by detecting the break character, and leaving an initial idle state and switching to at least one operating mode when the break character has been detected.

Abstract translation: 异步帧接收器包括用于接收包括断点字符的异步帧的输入，其包括具有相同值的确定数目的位。 一种热插拔电路，用于通过检测中断字符连接到正在运行的异步数据总线，并且当检测到断点字符时，保持初始空闲状态并切换到至少一个操作模式。

公开(公告)号：US20040243786A1

公开(公告)日：2004-12-02

申请号：US10814823

申请日：2004-03-31

Applicant: STMicroelectronics SA

Inventor： Franck Roche ,  Philippe Basset

IPC: G06F012/02

CPC classification number: G06F9/342

Abstract: A microprocessor includes a processing unit, an address bus connected to an addressable memory space, and executes instructions from an instruction set for accessing the addressable memory space. The addressable memory space is for a lower memory area and an extended memory area. The instruction set includes a first instruction group for accessing the lower memory area, and a second instruction group that is distinct from the first instruction group for accessing the extended memory area.

Abstract translation: 微处理器包括处理单元，连接到可寻址存储器空间的地址总线，并且执行来自用于访问可寻址存储器空间的指令集的指令。 可寻址存储器空间用于较低的存储区域和扩展存储区域。 指令集包括用于访问下部存储器区域的第一指令组和与用于访问扩展存储器区域的第一指令组不同的第二指令组。

公开(公告)号：US20040229454A1

公开(公告)日：2004-11-18

申请号：US10781565

申请日：2004-02-18

Applicant: STMICROELECTRONICS SA ,  KONINKLIJKE PHILIPS ELECTRONICS N.V.

Inventor： Joaquin Torres ,  Vincent Arnal ,  Laurent Gosset

IPC: H01L021/76

CPC classification number: H01L23/5329 ,  H01L21/7682 ,  H01L23/5222 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A process for fabricating an integrated electronic circuit comprises the formation of at least one air gap between interconnect elements above only a defined portion of a surface of a substrate, within an interconnect layer. The interconnect layer comprises a sacrificial material and extends beneath an intermediate layer of permeable material. The air gap is formed by removal, through the intermediate layer, of at least part of the sacrificial material by bringing the permeable material into contact with an agent for removing the sacrificial material, to which agent the permeable material is resistant.

Abstract translation: 一种用于制造集成电子电路的工艺包括在互连层内形成位于衬底表面的限定部分之上的互连元件之间的至少一个气隙。 互连层包括牺牲材料并在可渗透材料的中间层之下延伸。 通过使可渗透​​材料与用于除去牺牲材料的试剂接触而将可渗透材料抵抗的试剂与通过中间层去除至少部分牺牲材料形成气隙。