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    METHOD AND SYSTEM FOR IMPROVED VISIBILITY IN BLENDED LAYERS FOR HIGH DYNAMIC RANGE DISPLAYS
    83.
    发明公开
    METHOD AND SYSTEM FOR IMPROVED VISIBILITY IN BLENDED LAYERS FOR HIGH DYNAMIC RANGE DISPLAYS 审中-公开

    公开(公告)号：US20230267581A1

    公开(公告)日：2023-08-24

    申请号：US18309568

    申请日：2023-04-28

    Applicant: ATI Technologies ULC

    Inventor： Jie Zhou ,  David I.J. Glen

    IPC: G06T5/00 ,  H04N23/741

    CPC classification number: G06T5/009 ,  H04N23/741 ,  G06T2207/20208

    Abstract: There are many instances where a standard dynamic range (“SDR”) overlay is displayed over high dynamic range (“HDR”) content on HDR displays. Because the overlay is SDR, the maximum brightness of the overlay is much lower than the maximum brightness of the HDR content, which can lead to the SDR elements being obscured if those elements have at least some transparency. The present disclosure provides techniques including modifying the luminance of either or both of the HDR and SDR content when an SDR layer with some transparency is displayed over HDR content. A variety of techniques are provided. In one example, a fixed adjustment is applied to pixels of one or both of the SDR layer and the HDR layer. The fixed adjustment comprises decreasing the luminance of the HDR layer and/or increasing the luminance of the SDR layer. In another example, a variable adjustment is applied.

    Performing asynchronous memory clock changes on multi-display systems
    84.
    发明授权
    Performing asynchronous memory clock changes on multi-display systems 有权

    公开(公告)号：US11699408B2

    公开(公告)日：2023-07-11

    申请号：US17131209

    申请日：2020-12-22

    Applicant: ATI Technologies ULC

    Inventor： Arshad Rahman ,  Rajeevan Panchacharamoorthy ,  Boris Ivanovic

    IPC: G09G3/36 ,  G09G5/00 ,  G11C7/22 ,  G11C7/10

    CPC classification number: G09G3/3618 ,  G09G5/001 ,  G09G5/006 ,  G11C7/1072 ,  G11C7/222

    Abstract: Systems, apparatuses, and methods for performing asynchronous memory clock changes on multiple displays are disclosed. From time to time, a memory clock frequency change is desired for a memory subsystem storing frame buffer(s) used to drive pixels to multiple displays. For example, when the real-time memory bandwidth demand differs from the memory bandwidth available with the existing memory clock frequency, a control unit tracks the vertical blanking interval (VBI) timing of a first display. Also, the control unit causes a second display to enter into panel self-refresh (PSR) mode. Once the PSR mode of the second display overlaps with a VBI of the first display, a memory clock frequency change, including memory training, is initiated. After the memory clock frequency change, the displays are driven by the frame buffer(s) in the memory subsystem at an updated frequency.

    UPDATING SHADER SCHEDULING POLICY AT RUNTIME
    87.
    发明公开
    UPDATING SHADER SCHEDULING POLICY AT RUNTIME 审中-公开

    公开(公告)号：US20230206537A1

    公开(公告)日：2023-06-29

    申请号：US17562884

    申请日：2021-12-27

    Applicant: Advanced Micro Devices, Inc. ,  ATI Technologies ULC

    Inventor： Thomas Daniel Perry ,  Steven John Tovey ,  Mehdi Saeedi

    IPC: G06T15/00 ,  A63F13/52

    CPC classification number: G06T15/005 ,  A63F13/52

    Abstract: Systems, apparatuses, and methods for updating and optimizing task scheduling policies are disclosed. A new policy is obtained and updated at runtime by a client based on a server analyzing a wide spectrum of telemetry data on a relatively long time scale. Instead of only looking at the telemetry data from the client's execution of tasks for the previous frame, the server analyzes the execution times of tasks for multiple previous frames so as to determine a more optimal policy for subsequent frames. This mechanism enables making a more informed task scheduling policy decision as well as customizing the policy per application, game, and user without requiring a driver update. Also, this mechanism facilitates improved load balancing across the various processing engines, each of which has their own task queues. The improved load balancing is achieved by analyzing the telemetry data including resource utilization statistics for the different processing engines.

    CACHE BLOCKING FOR DISPATCHES
    89.
    发明公开
    CACHE BLOCKING FOR DISPATCHES 审中-公开

    公开(公告)号：US20230205698A1

    公开(公告)日：2023-06-29

    申请号：US17564474

    申请日：2021-12-29

    Applicant: ADVANCED MICRO DEVICES, INC. ,  ATI TECHNOLOGIES ULC

    Inventor： Saurabh SHARMA ,  Hashem HASHEMI ,  Paavo PESSI ,  Mika TUOMI ,  Gianpaolo TOMMASI ,  Jeremy LUKACS ,  Guennadi RIGUER

    IPC: G06F12/0855

    CPC classification number: G06F12/0855 ,  G06F2212/1008

    Abstract: A processing system divides successive dispatches of work items into portions. The successive dispatches are separated from each other by barriers, each barrier indicating that the work items of the previous dispatch must complete execution before work items of a subsequent dispatch can begin execution. In some embodiments, the processing system interleaves execution of portions of a first dispatch with portions of subsequent dispatches that consume data produced by the first dispatch. The processing system thereby reduces the amount of data written to the local cache by a producer dispatch while preserving data locality for a subsequent consumer (or consumer/producer) dispatch and facilitating processing efficiency.

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