公开(公告)号：US20100244203A1

公开(公告)日：2010-09-30

申请号：US12678978

申请日：2008-11-09

Applicant: Chantal Arena

Inventor： Chantal Arena

IPC: H01L29/06 ,  H01L21/205

CPC classification number: H01L21/02389 ,  H01L21/02447 ,  H01L21/02458 ,  H01L21/02472 ,  H01L21/02488 ,  H01L21/0254

Abstract: A semiconductor structure includes a substrate having a first nitride-based semiconductor layer. A pseudomorphic protective layer is formed on the first nitride-based semiconductor layer and a second nitride-based semiconductor layer is formed on the pseudomorphic protective layer. The pseudomorphic protective layer has a thickness that is less than a critical thickness so that it drives the material quality of the second nitride-based semiconductor layer to correspond with that of the first nitride-based semiconductor layer.

Abstract translation: 半导体结构包括具有第一氮化物基半导体层的衬底。 在第一氮化物基半导体层上形成假形保护层，在伪晶保护层上形成第二氮化物系半导体层。 假形保护层的厚度小于临界厚度，从而驱动第二氮化物基半导体层的材料质量与第一氮化物基半导体层的材料质量相对应。

公开(公告)号：US20100244197A1

公开(公告)日：2010-09-30

申请号：US12721461

申请日：2010-03-10

Applicant: Chantal Arena ,  Laurent Clavelier ,  Marc Rabarot

Inventor： Chantal Arena ,  Laurent Clavelier ,  Marc Rabarot

IPC: H01L29/20 ,  H01L21/302

CPC classification number: H01L29/2003 ,  H01L21/0242 ,  H01L21/0243 ,  H01L21/02458 ,  H01L21/0254 ,  H01L21/02639

Abstract: The invention provides methods and structures for reducing surface dislocations of a semiconductor layer, and can be employed during the epitaxial growth of semiconductor structures and layers comprising III-nitride materials. Embodiments involve the formation of a plurality of dislocation pit plugs to prevent propagation of dislocations from an underlying layer of material into a following semiconductor layer of material.

Abstract translation: 本发明提供了用于减少半导体层的表面位错的方法和结构，并且可以在半导体结构和包含III族氮化物材料的层的外延生长期间使用。 实施例涉及形成多个位错坑塞，以防止位错从材料的下层扩散到随后的材料半导体层中。

公开(公告)号：US07790048B2

公开(公告)日：2010-09-07

申请号：US11433713

申请日：2006-05-12

Applicant: Frédéric Allibert ,  François Brunier

Inventor： Frédéric Allibert ,  François Brunier

IPC: B44C1/22 ,  C23F1/00

CPC classification number: H01L22/34 ,  H01L2924/0002 ,  H01L2924/00

Abstract: The invention relates to a method for forming a plurality of electrically conductive islands in a working layer of a multilayer structure made from semiconductor materials, with the structure including an electrically insulating layer located beneath the working layer. This method includes the steps of selectively masking certain regions of the working layer in order to define several islands therein, with each region masked from the working layer corresponding to a respective island, and then wet chemical etching of the masked working layer to form a plurality of working layer islands each surrounded by the electrically insulating layer. The invention also proposes the application of such a method to the characterization of the electrical properties of a structure, and an associated device.

Abstract translation: 本发明涉及一种用于在由半导体材料制成的多层结构的工作层中形成多个导电岛的方法，其结构包括位于工作层下方的电绝缘层。 该方法包括以下步骤：选择性地掩蔽工作层的某些区域以便在其中限定几个岛，其中每个区域从工作层被掩蔽，对应于相应的岛，然后湿式化学蚀刻掩蔽的工作层以形成多个 的工作层岛，每个被电绝缘层包围。 本发明还提出了这种方法用于表征结构和相关联的装置的电性能的应用。

公开(公告)号：US07772127B2

公开(公告)日：2010-08-10

申请号：US11267494

申请日：2005-11-03

Applicant: Christophe Figuet ,  Mark Kennard

Inventor： Christophe Figuet ,  Mark Kennard

IPC: H01L21/31 ,  H01L21/469

CPC classification number: H01L21/76254 ,  H01L21/02381 ,  H01L21/0245 ,  H01L21/02494 ,  H01L21/02502 ,  H01L21/0251 ,  H01L21/02524 ,  H01L21/02532 ,  H01L21/02587 ,  H01L21/0262

Abstract: The invention relates to a method for forming a semiconductor heterostructure by providing a substrate with a first in-plane lattice parameter a1, providing a buffer layer with a second in-plane lattice parameter a2 and providing a top layer over the buffer layer. In order to improve the surface roughness of the semiconductor heterostructure, an additional layer is provided in between the buffer layer and the top layer, wherein the additional layer has a third in-plane lattice parameter a3 which is in between the first and second lattice parameters.

Abstract translation: 本发明涉及一种用于通过向第一面内晶格参数a1提供衬底来形成半导体异质结构的方法，为缓冲层提供第二面内晶格参数a2并在缓冲层上提供顶层。 为了改善半导体异质结构的表面粗糙度，在缓冲层和顶层之间提供附加层，其中附加层具有在第一和第二晶格参数之间的第三面内晶格参数a3 。

公开(公告)号：US20100190416A1

公开(公告)日：2010-07-29

申请号：US12657842

申请日：2010-01-28

Applicant: Walter Schwarzenbach ,  Sebastien Kerdiles ,  Aziz Alami-Idrissi

Inventor： Walter Schwarzenbach ,  Sebastien Kerdiles ,  Aziz Alami-Idrissi

IPC: B24B9/06 ,  B24B7/20

CPC classification number: B24B9/065 ,  B24B37/042 ,  B24B37/28 ,  H01L21/02032 ,  H01L21/02079 ,  H01L21/76254

Abstract: Disclosed are devices and methods for chemical and mechanical polishing of the edge of a semiconductor substrate that includes a protruding residual topography in a peripheral region of the substrate resulting from a layer transfer process based on an ion implantation step, a bonding step and a detachment step, such as Smart-Cut™. To be able to remove this step-like region, exemplary devices include a polishing pad, wherein the polishing pad is arranged and configured such that its cross section in a plane perpendicular to the surface of a substrate holder is curved. The disclosure furthermore relates to a pad holder used certain exemplary devices and methods for polishing a semiconductor substrate that has a protruding residual topography.

Abstract translation: 公开了一种半导体衬底的边缘的化学和机械抛光的装置和方法，其包括基于离子注入步骤的层转移工艺所产生的衬底的外围区域中的突出的残留形貌，接合步骤和剥离步骤 ，如Smart-Cut™。 为了能够去除该阶梯状区域，示例性的装置包括抛光垫，其中抛光垫被布置和构造成使得其在垂直于衬底保持器的表面的平面中的横截面是弯曲的。 本发明还涉及使用某些用于抛光具有突出残留形貌的半导体衬底的示例性装置和方法的焊盘固定架。

公开(公告)号：US20100187568A1

公开(公告)日：2010-07-29

申请号：US12610092

申请日：2009-10-30

Applicant: Chantal ARENA

Inventor： Chantal ARENA

IPC: H01L29/20 ,  H01L21/20

CPC classification number: H01L29/2003 ,  H01L21/0242 ,  H01L21/02458 ,  H01L21/0254 ,  H01L21/0262 ,  H01L21/02639 ,  H01L21/02647 ,  H01L21/0265

Abstract: Methods and structures for producing semiconductor materials, substrates and devices with improved characteristics are disclosed. Structures and methods for forming reduced strain structures include forming a plurality of substantially strain-relaxed island structures and utilizing such island structures for subsequent further growth of strain-relaxed substantial continuous layers of semiconductor material.

Abstract translation: 公开了用于制造具有改进特性的半导体材料，衬底和器件的方法和结构。 用于形成减小的应变结构的结构和方法包括形成多个基本上应变松弛的岛结构，并利用这种岛状结构随后进一步生长应变松弛的基本连续的半导体材料层。

公开(公告)号：US07740735B2

公开(公告)日：2010-06-22

申请号：US11567417

申请日：2006-12-06

Applicant: Sebastien Kerdiles ,  Yves-Matthieu Le Vaillant

Inventor： Sebastien Kerdiles ,  Yves-Matthieu Le Vaillant

IPC: B32B38/10

CPC classification number: H01L21/68707 ,  G01N19/04 ,  H01L21/67092 ,  Y10S156/943 ,  Y10T29/53683 ,  Y10T83/0267 ,  Y10T156/1132 ,  Y10T156/1168 ,  Y10T156/1978 ,  Y10T156/1983

Abstract: A tool and method for disuniting two wafers, wherein at least one of the wafers is used in fabricating substrates for microelectronics, optoelectronics, or optics. The method includes the steps of temporarily affixing two gripper members to respective opposite faces of the wafers; and sufficiently displacing one of the gripper members relative to the other for inducing controlled flexing in at least one of the members and for exerting a force close to one edge of the wafers to assist in disuniting the wafers. If desired, the bonding energy between two wafers can be determined by measuring the force exerted during the displacement step or measuring the separation of the wafers while performing the disuniting operation.

Abstract translation: 一种用于分离两个晶片的工具和方法，其中至少一个晶片用于制造用于微电子学，光电子学或光学器件的衬底。 该方法包括以下步骤：将两个夹持件暂时固定到晶片的各个相对面上; 并且相对于另一个充分地移动夹持构件中的一个，用于在至少一个构件中引起受控的弯曲并且用于施加接近晶片的一个边缘的力以帮助使晶片脱离。 如果需要，可以通过测量在位移步骤期间施加的力或在执行分离操作时测量晶片的分离来确定两个晶片之间的结合能。

公开(公告)号：US20100127353A1

公开(公告)日：2010-05-27

申请号：US12610065

申请日：2009-10-30

Applicant: Fabrice LETERTRE ,  Jean-Marc BETHOUX ,  Alice BOUSSAGOL

Inventor： Fabrice LETERTRE ,  Jean-Marc BETHOUX ,  Alice BOUSSAGOL

IPC: H01L29/20 ,  H01L21/20

CPC classification number: H01L21/0242 ,  H01L21/02458 ,  H01L21/02472 ,  H01L21/0254 ,  H01L21/76254

Abstract: Composite substrates are produced that include a strained III-nitride material seed layer on a support substrate. Methods of producing the composite substrate include developing a desired lattice strain in the III-nitride material to produce a lattice parameter substantially matching a lattice parameter of a device structure to be formed on the composite substrate. The III-nitride material may be formed with a Ga polarity or a N polarity. The desired lattice strain may be developed by forming a buffer layer between the III-nitride material and a growth substrate, implanting a dopant in the III-nitride material to modify its lattice parameter, or forming the III-nitride material with a coefficient of thermal expansion (CTE) on a growth substrate with a different CTE.

Abstract translation: 生产复合衬底，其包括在支撑衬底上的应变III族氮化物材料种子层。 制造复合衬底的方法包括在III族氮化物材料中开发所需的晶格应变，以产生基本上与要在复合衬底上形成的器件结构的晶格参数匹配的晶格参数。 III族氮化物材料可以形成为Ga极性或N极性。 可以通过在III族氮化物材料和生长衬底之间形成缓冲层来形成所需的晶格应变，在III族氮化物材料中注入掺杂剂以改变其晶格参数，或者用热系数形成III族氮化物材料 在具有不同CTE的生长衬底上的膨胀（CTE）。

公开(公告)号：US20100109126A1

公开(公告)日：2010-05-06

申请号：US12576116

申请日：2009-10-08

Applicant: Chantal ARENA

Inventor： Chantal ARENA

IPC: H01L21/20 ,  H01L29/20

CPC classification number: H01L21/0254 ,  H01L21/0242 ,  H01L21/02458 ,  H01L21/02488 ,  H01L21/02647 ,  H01L21/76254 ,  H01L29/0684 ,  H01L29/2003

Abstract: Methods of fabricating semiconductor devices or structures include forming structures of a semiconductor material overlying a layer of a compliant material, subsequently changing the viscosity of the compliant material to relax the semiconductor material structures, and utilizing the relaxed semiconductor material structures as a seed layer in forming a continuous layer of relaxed semiconductor material. In some embodiments, the layer of semiconductor material may comprise a III-V type semiconductor material, such as, for example, indium gallium nitride. Novel intermediate structures are formed during such methods. Engineered substrates include a continuous layer of semiconductor material having a relaxed lattice structure.

Abstract translation: 制造半导体器件或结构的方法包括形成覆盖柔性材料层的半导体材料的结构，随后改变柔顺材料的粘度以使半导体材料结构松弛，并且利用松弛的半导体材料结构作为晶种层形成 连续的松弛半导体材料层。 在一些实施例中，半导体材料层可以包括III-V型半导体材料，例如氮化铟镓。 在这种方法中形成了新的中间结构。 工程衬底包括具有松弛晶格结构的连续的半导体材料层。

公开(公告)号：US20100044706A1

公开(公告)日：2010-02-25

申请号：US12535056

申请日：2009-08-04

Applicant: Xavier Hebras

Inventor： Xavier Hebras

IPC: H01L29/24

CPC classification number: H01L21/76254

Abstract: Various structures that include at least one thin layer of an amorphous material on a supporting substrate. One structure generally has a receiving substrate, a central crystalline layer and an amorphous layer, all of which may lack any end of range point defects. Another structure includes an intermediate substrate having an upper face, an upper portion and a lower portion, an amorphous layer that does not contain end of range point defects, and a first crystalline layer containing end of range point defects subjacent the amorphous layer and located in the lower portion; and a supporting substrate bonded to the upper face of the intermediate substrate. That structure can also contain a weakened zone or porous layer to facilitate removal of the first crystalline layer to provide the amorphous layer as an upper layer of the semiconductor structure.

Abstract translation: 在支撑衬底上包括非晶材料的至少一个薄层的各种结构。 一个结构通常具有接收衬底，中心结晶层和非晶层，所有这些都可能缺少范围点缺陷的任何结束。 另一种结构包括具有上表面，上部分和下部分的中间衬底，不包含端点缺陷终点的非晶层，以及包含位于非晶层下面的范围点缺陷末端的第一结晶层，并位于 下部 以及与中间基板的上表面接合的支撑基板。 该结构还可以包含弱化区或多孔层，以有助于去除第一晶体层以提供作为半导体结构的上层的非晶层。