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    Selective NiGe wet etch for transistors with Ge body and/or Ge source/drain extensions
    82.
    发明授权
    Selective NiGe wet etch for transistors with Ge body and/or Ge source/drain extensions 有权
    具有Ge体和/或Ge源极/漏极延伸的晶体管的选择性NiGe湿法蚀刻

    公开(公告)号：US06703291B1

    公开(公告)日：2004-03-09

    申请号：US10322390

    申请日：2002-12-17

    Applicant: Boyan Boyanov ,  Steven Keating ,  Anand Murthy

    Inventor： Boyan Boyanov ,  Steven Keating ,  Anand Murthy

    IPC: H01L2974

    CPC classification number: H01L29/665 ,  C23F1/26 ,  H01L21/28255 ,  H01L21/28518 ,  H01L21/32134 ,  H01L21/324

    Abstract: The wet etch stage of the salicide process normally used to fabricate polysilicon and silicon-based semiconductor transistors may not be appropriate for germanium-based transistors because the wet etch chemicals at such temperatures will dissolve the germanium leaving no source, gate, or drain for the transistor. In embodiments of the invention, nickel is blanket deposited over the source, drain, and gate regions of the germanium-based transistor, annealed to cause the nickel to react with the germanium, and wet etched to remove un-reacted nickel from dielectric regions (e.g., shallow trench isolation (STI) regions) but leave NiGe in the source, gate, and drain regions. The wet etch is a mild oxidizing solution at room temperature.

    Abstract translation: 通常用于制造多晶硅和硅基半导体晶体管的自对准硅化物工艺的湿蚀刻阶段可能不适用于基于锗的晶体管，因为在这样的温度下的湿蚀刻化学品将溶解锗，不会留下源，栅极或漏极 晶体管。 在本发明的实施例中，镍被覆盖地沉积在锗基晶体管的源极，漏极和栅极区域上，退火以使镍与锗反应，并进行湿式蚀刻以从电介质区域去除未反应的镍（ 例如浅沟槽隔离（STI）区域），而在源极，栅极和漏极区域留下NiGe。 湿蚀刻在室温下是温和的氧化溶液。

    CMOS transistor junction regions formed by a CVD etching and deposition sequence
    85.
    发明授权
    CMOS transistor junction regions formed by a CVD etching and deposition sequence 有权
    通过CVD蚀刻和沉积顺序形成CMOS晶体管结区域

    公开(公告)号：US07812394B2

    公开(公告)日：2010-10-12

    申请号：US12250191

    申请日：2008-10-13

    Applicant: Anand Murthy ,  Glenn A. Glass ,  Andrew N. Westmeyer ,  Michael L. Hattendorf ,  Jeffrey R. Wank

    Inventor： Anand Murthy ,  Glenn A. Glass ,  Andrew N. Westmeyer ,  Michael L. Hattendorf ,  Jeffrey R. Wank

    IPC: H01L31/119

    CPC classification number: H01L29/7848 ,  H01L21/02381 ,  H01L21/02532 ,  H01L21/0262 ,  H01L21/02639 ,  H01L29/517 ,  H01L29/66628 ,  H01L29/7834

    Abstract: This invention adds to the art of replacement source-drain cMOS transistors. Processes may involve etching a recess in the substrate material using one equipment set, then performing deposition in another. Disclosed is a method to perform the etch and subsequent deposition in the same reactor without atmospheric exposure. In-situ etching of the source-drain recess for replacement source-drain applications provides several advantages over state of the art ex-situ etching. Transistor drive current is improved by: (1) Eliminating contamination of the silicon-epilayer interface when the as-etched surface is exposed to atmosphere and (2) Precise control over the shape of the etch recess. Deposition may be done by a variety of techniques including selective and non-selective methods. In the case of blanket deposition, a measure to avoid amorphous deposition in performance critical regions is also presented.

    Abstract translation: 本发明增加了替代源极 - 漏极cMOS晶体管的技术。 方法可以包括使用一个设备组来蚀刻衬底材料中的凹部，然后在另一个设备组中进行沉积。 公开了一种在没有大气暴露的情况下在相同的反应器中进行蚀刻和随后的沉积的方法。 用于替代源极 - 漏极应用的源极 - 漏极凹槽的原位蚀刻提供了优于现有技术的非原位蚀刻的几个优点。 晶体管驱动电流通过以下因素得到改善：（1）当被蚀刻的表面暴露于大气中时，消除硅 - 外延层界面的污染，（2）精确控制蚀刻凹槽的形状。 沉积可以通过各种技术进行，包括选择性和非选择性方法。 在覆盖层沉积的情况下，还提出了避免在性能关键区域中无定形沉积的措施。

    CMOS device and method of manufacturing same
    86.
    发明授权
    CMOS device and method of manufacturing same 有权
    CMOS器件及其制造方法

    公开(公告)号：US07663192B2

    公开(公告)日：2010-02-16

    申请号：US12215989

    申请日：2008-06-30

    Applicant: Bernhard Sell ,  Anand Murthy ,  Mark Liu ,  Daniel Aubertine

    Inventor： Bernhard Sell ,  Anand Murthy ,  Mark Liu ,  Daniel Aubertine

    IPC: H01L27/092

    CPC classification number: H01L21/823807 ,  H01L21/823814 ,  H01L21/823828 ,  H01L21/823835 ,  H01L29/66628 ,  H01L29/7834

    Abstract: A CMOS device includes NMOS (110) and PMOS (130) transistors, each of which include a gate electrode (111, 131) and a gate insulator (112, 132) that defines a gate insulator plane (150, 170). The transistors each further include source/drain regions (113/114, 133/134) having a first portion (115, 135) below the gate insulator plane and a second portion (116, 136) above the gate insulator plane, and an electrically insulating material (117). The NMOS transistor further includes a blocking layer (121) having a portion (122) between the gate electrode and a source contact (118) and a portion (123) between the gate electrode and a drain contact (119). The PMOS transistor further includes a blocking layer (141) having a portion (142) between the source region and the insulating material and a portion (143) between the drain region and the insulating material.

    Abstract translation: CMOS器件包括NMOS（110）和PMOS（130）晶体管，每个晶体管包括限定栅极绝缘体平面（150,170）的栅电极（111,131）和栅极绝缘体（112,132）。 晶体管每个还包括具有栅极绝缘体平面下方的第一部分（115,135）和栅极绝缘体平面上方的第二部分（116,136）的源/漏区（113/114,133 / 134） 绝缘材料（117）。 NMOS晶体管还包括阻挡层（121），其具有在栅电极和源极触点（118）之间的部分（122）和栅极电极和漏极触点（119）之间的部分（123）。 所述PMOS晶体管还包括阻挡层（141），所述阻挡层（141）具有在所述源极区域和所述绝缘材料之间的部分（142）以及所述漏极区域和所述绝缘材料之间的部分（143）。

    Method for fabricating a heterojunction bipolar transistor
    87.
    发明授权
    Method for fabricating a heterojunction bipolar transistor 有权
    异质结双极晶体管的制造方法

    公开(公告)号：US07517768B2

    公开(公告)日：2009-04-14

    申请号：US10404781

    申请日：2003-03-31

    Applicant: Ravindra Soman ,  Anand Murthy ,  Peter VanDerVoorn ,  Shahriar Ahmed

    Inventor： Ravindra Soman ,  Anand Murthy ,  Peter VanDerVoorn ,  Shahriar Ahmed

    IPC: H01L21/331

    CPC classification number: H01L29/66242

    Abstract: A bipolar transistor with a SiGe:C film and a seed layer forming beneath the SiGe:C film and methods of making same. The method includes placing a substrate in a reactor chamber and introducing a silicon source gas into the reactor chamber to form a silicon seed layer. The reactor chamber is maintained at a pressure below 45 Torr and a temperature between about 700° C. and 850° C. After the seed layer is formed, the silicon source gas is stopped. The reactor chamber is then simultaneously adjusted to a pressure between about 70 Torr and 90 Torr and a temperature between about 600° C. and 650° C. The silicon source gas, a germanium source gas, and a carbon source gas are introduced to form the SiGe:C film on the seed layer.

    Abstract translation: 具有SiGe：C膜的双极晶体管和形成在SiGe：C薄膜下面的晶种层及其制造方法。 该方法包括将基板放置在反应器室中并将硅源气体引入反应器室以形成硅籽晶层。 反应室保持在低于45托的压力和约700℃至850℃之间的温度。形成种子层之后，停止硅源气体。 然后将反应器室同时调节至约70托和90托之间的压力以及约600℃和650℃之间的温度。引入硅源气体，锗源气体和碳源气体以形成 种子层上的SiGe：C膜。

    Selective etch for patterning a semiconductor film deposited non-selectively
    89.
    发明授权
    Selective etch for patterning a semiconductor film deposited non-selectively 有权
    用于图案化非选择性沉积的半导体膜的选择性蚀刻

    公开(公告)号：US07364976B2

    公开(公告)日：2008-04-29

    申请号：US11387012

    申请日：2006-03-21

    Applicant: Willy Rachmady ,  Anand Murthy

    Inventor： Willy Rachmady ,  Anand Murthy

    IPC: H01L21/336

    CPC classification number: H01L29/7848 ,  H01L21/32134 ,  H01L29/165 ,  H01L29/66628 ,  H01L29/66636

    Abstract: A method to selectively etch, and hence pattern, a semiconductor film deposited non-selectively is described. In one embodiment, a carbon-doped silicon film is deposited non-selectively such that the film forms an epitaxial region where deposited on a crystalline surface and an amorphous region where deposited on an amorphous surface. A four-component wet etch mixture is tuned to selectively etch the amorphous region while retaining the epitaxial region, wherein the four-component wet etch mixture comprises an oxidizing agent, an etchant, a buffer and a diluent.

    Abstract translation: 描述了非选择性地沉积半导体膜并因此图案化的方法。 在一个实施例中，碳掺杂硅膜被非选择性地沉积，使得膜形成沉积在沉积在非晶表面上的结晶表面和非晶区域上的外延区域。 调节四组分湿蚀刻混合物以选择性地蚀刻非晶区域同时保留外延区域，其中四组分湿蚀刻混合物包含氧化剂，蚀刻剂，缓冲剂和稀释剂。

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