公开(公告)号：US08658530B2

公开(公告)日：2014-02-25

申请号：US13612240

申请日：2012-09-12

Applicant: Marwan H. Khater ,  Christian Lavoie ,  Bin Yang ,  Zhen Zhang

Inventor： Marwan H. Khater ,  Christian Lavoie ,  Bin Yang ,  Zhen Zhang

IPC: H01L21/4763 ,  H01L21/477 ,  H01L21/36

CPC classification number: H01L29/7839 ,  H01L21/28052 ,  H01L21/28537 ,  H01L29/47 ,  H01L29/665 ,  H01L29/66643 ,  H01L29/66772 ,  H01L29/78618

Abstract: An epitaxial Ni silicide film that is substantially non-agglomerated at high temperatures, and a method for forming the epitaxial Ni silicide film, is provided. The Ni silicide film of the present disclosure is especially useful in the formation of ETSOI (extremely thin silicon-on-insulator) Schottky junction source/drain FETs. The resulting epitaxial Ni silicide film exhibits improved thermal stability and does not agglomerate at high temperatures.

Abstract translation: 提供了在高温下基本上未附聚的外延Ni硅化物膜，以及形成外延Ni硅化物膜的方法。 本公开的Ni硅化物膜特别可用于形成ETSOI（极薄的绝缘体上硅）肖特基结源极/漏极FET。 得到的外延Ni硅化物膜具有改善的热稳定性，并且在高温下不聚结。

公开(公告)号：US20140038402A1

公开(公告)日：2014-02-06

申请号：US13563202

申请日：2012-07-31

Applicant: Andy C. Wei ,  Bin Yang ,  Francis M. Tambwe

Inventor： Andy C. Wei ,  Bin Yang ,  Francis M. Tambwe

IPC: H01L21/336 ,  H01L21/311

CPC classification number: H01L27/11 ,  H01L21/823821 ,  H01L29/7843

Abstract: A method for fabricating a dual-workfunction FinFET structure includes depositing a first workfunction material in a layer in a plurality of trenches of the FinFET structure, depositing a low-resistance material layer over the first workfunction material layer, and etching the low-resistance material layer and the first workfunction material layer from a portion of the FinFET structure. The method further includes depositing a second workfunction material in a layer in a plurality of trenches of the portion and depositing a stress material layer over the second workfunction material layer.

Abstract translation: 一种用于制造双功函数FinFET结构的方法，包括在FinFET结构的多个沟槽中的层中沉积第一功函数材料，在第一功函数材料层上沉积低电阻材料层，以及蚀刻低电阻材料 层和来自FinFET结构的一部分的第一功函数材料层。 该方法还包括在该部分的多个沟槽中的层中沉积第二功函数材料，并在第二功函数材料层上沉积应力材料层。

公开(公告)号：US08580541B2

公开(公告)日：2013-11-12

申请号：US12962366

申请日：2010-12-07

Applicant: Bin Yang ,  Charles E. Wyman

Inventor： Bin Yang ,  Charles E. Wyman

IPC: C12P7/06 ,  C12P7/08 ,  C12P7/10 ,  C12P19/14 ,  C12P21/06 ,  C07K14/415 ,  C07K14/765

CPC classification number: C12P7/08 ,  C12P7/10 ,  C12P19/02 ,  Y02E50/16 ,  Y02E50/17

Abstract: Disclosed is a method for converting cellulose in a lignocellulosic biomass. The method provides for a lignin-blocking polypeptide and/or protein treatment of high lignin solids. The treatment enhances cellulase availability in cellulose conversion and allows for the determination of optimized pretreatment conditions. Additionally, ethanol yields from a Simultaneous Saccharification and Fermentation process are improved 5-25% by treatment with a lignin-blocking polypeptide and/or protein.

Abstract translation: 公开了一种在木质纤维素生物质中转化纤维素的方法。 该方法提供高木质素固体的木质素阻断多肽和/或蛋白质处理。 该处理增强了纤维素转化中的纤维素酶可用性，并且允许确定优化的预处理条件。 此外，通过用木质素阻断多肽和/或蛋白质处理，来自同时糖化和发酵过程的乙醇产率提高了5-25％。

公开(公告)号：US20130292767A1

公开(公告)日：2013-11-07

申请号：US13465064

申请日：2012-05-07

Applicant: Bin Yang ,  Xia Li ,  Jun Yuan

Inventor： Bin Yang ,  Xia Li ,  Jun Yuan

IPC: H01L27/12 ,  H01L21/8238

CPC classification number: H01L21/823814 ,  H01L21/28026 ,  H01L21/823828 ,  H01L21/84 ,  H01L27/1203 ,  H01L27/1211 ,  H01L29/1054 ,  H01L29/165 ,  H01L29/42376 ,  H01L29/47 ,  H01L29/66545 ,  H01L29/66621 ,  H01L29/66628 ,  H01L29/66636 ,  H01L29/7834

Abstract: A complementary metal-oxide-semiconductor (CMOS) device and methods of formation thereof are disclosed. In a particular embodiment, a CMOS device includes a silicon substrate, a dielectric insulator material on the silicon substrate, and an extension layer on the dielectric insulator material. The CMOS device further includes a gate in contact with a channel and in contact with an extension region. The CMOS device also includes a source in contact with the extension region and a drain in contact with the extension region. The extension region includes a first region in contact with the source and the gate and includes a second region in contact with the drain and the gate.

Abstract translation: 公开了一种互补金属氧化物半导体（CMOS）器件及其形成方法。 在特定实施例中，CMOS器件包括硅衬底，硅衬底上的介电绝缘体材料以及介电绝缘体材料上的延伸层。 CMOS器件还包括与沟道接触并与延伸区域接触的栅极。 CMOS器件还包括与延伸区域接触的源极和与延伸区域接触的漏极。 延伸区域包括与源极和栅极接触的第一区域，并且包括与漏极和栅极接触的第二区域。

公开(公告)号：US08507369B2

公开(公告)日：2013-08-13

申请号：US13659907

申请日：2012-10-24

Applicant: Xubin Jing ,  Bin Yang ,  Mingsheng Guo

Inventor： Xubin Jing ,  Bin Yang ,  Mingsheng Guo

IPC: H01L21/00

CPC classification number: H01L29/66083 ,  B82Y10/00 ,  B82Y40/00 ,  H01L29/0673 ,  H01L29/0692 ,  H01L29/16 ,  H01L29/413 ,  H01L29/66439 ,  H01L29/775

Abstract: The invention provides a method for producing silicon nanowire devices, including the following steps: growing SiNW on a substrate; depositing an amorphous carbon layer and dielectric anti-reflectivity coating orderly; removing part of dielectric anti-reflectivity coating and amorphous carbon layer above the SiNW through dry etching to expose the SiNW device area; depositing an oxide film on the surface of the above structure; forming a metal pad connected with the SiNW in the SiNW device area; depositing a passivation layer on the surface of the above structure; applying photolithography and etching technology to form contact holes on the metal pad and to remove the passivation layer, the oxide film and the dielectric anti-reflectivity coating above the SiNW outside the device area, stopping on the amorphous carbon layer; removing the amorphous carbon layer above the SiNW outside the device area through ashing process to expose the SiNW.

Abstract translation: 本发明提供一种生产硅纳米线器件的方法，包括以下步骤：在衬底上生长SiNW; 有序沉积无定形碳层和电介质抗反射涂层; 通过干蚀刻去除SiNW上方的介电抗反射涂层和无定形碳层的一部分，以暴露SiNW器件区域; 在上述结构的表面上沉积氧化膜; 在SiNW器件区域中形成与SiNW连接的金属焊盘; 在上述结构的表面上沉积钝化层; 施加光刻和蚀刻技术以在金属焊盘上形成接触孔，并在器件区域外的SiNW上方去除钝化层，氧化物膜和介电抗反射涂层，停止在无定形碳层上; 通过灰化处理去除器件区域外的SiNW以上的无定形碳层，以暴露SiNW。

公开(公告)号：US08486914B2

公开(公告)日：2013-07-16

申请号：US12750655

申请日：2010-03-30

Applicant: Chi-Huey Wong ,  Alice L. Yu ,  Wen-Bin Yang ,  Eugene Fan ,  Hsien-Yeh Hsu ,  Peishan Lee ,  Tseng-Rong Tu ,  Chin-Chung Hung

Inventor： Chi-Huey Wong ,  Alice L. Yu ,  Wen-Bin Yang ,  Eugene Fan ,  Hsien-Yeh Hsu ,  Peishan Lee ,  Tseng-Rong Tu ,  Chin-Chung Hung

IPC: A61K31/715

CPC classification number: A61K31/715

Abstract: Compositions comprising Hirsutella sinensis mycelia extracts and chromatographically separated polysaccharide-enriched fractions thereof are provided. Methods for extracting Hirsutella sinensis mycelia are provided. Compositions for methods for their use in amelioration, prevention and treatment of sepsis, acute endotoxemia and inflammatory responses are disclosed.

Abstract translation: 提供了包含中华绒螯蟹菌丝体提取物和色谱分离的多糖富集部分的组合物。 提供了中华绒螯蟹提取物的方法。 公开了其用于改善，预防和治疗败血症，急性内毒素血症和炎性反应的方法的组合物。

公开(公告)号：US08482084B2

公开(公告)日：2013-07-09

申请号：US12726789

申请日：2010-03-18

Applicant: Marwan H. Khater ,  Christian Lavoie ,  Bin Yang ,  Zhen Zhang

Inventor： Marwan H. Khater ,  Christian Lavoie ,  Bin Yang ,  Zhen Zhang

IPC: H01L29/76 ,  H01L31/00

CPC classification number: H01L29/78654 ,  H01L29/7839

Abstract: A Schottky field effect transistor is provided that includes a substrate having a layer of semiconductor material atop a dielectric layer, wherein the layer of semiconductor material has a thickness of less than 10.0 nm. A gate structure is present on the layer of semiconductor material. Raised source and drain regions comprised of a metal semiconductor alloy are present on the layer of semiconductor material on opposing sides of the gate structure. The raised source and drain regions are Schottky source and drain regions. In one embodiment, a first portion of the Schottky source and drain regions that is adjacent to a channel region of the Schottky field effect transistor contacts the dielectric layer, and a non-reacted semiconductor material is present between a second portion of the Schottky source and drain regions and the dielectric layer.

Abstract translation: 提供一种肖特基场效应晶体管，其包括在电介质层顶上具有半导体材料层的衬底，其中半导体材料层的厚度小于10.0nm。 栅极结构存在于半导体材料层上。 在栅极结构的相对侧的半导体材料层上存在由金属半导体合金构成的凸起的源极和漏极区域。 凸起的源极和漏极区域是肖特基源极和漏极区域。 在一个实施例中，与肖特基场效应晶体管的沟道区相邻的肖特基源极和漏极区的第一部分接触电介质层，并且未反应的半导体材料存在于肖特基源的第二部分和 漏区和电介质层。

公开(公告)号：US20130102049A1

公开(公告)日：2013-04-25

申请号：US13548181

申请日：2012-07-12

Applicant: Wen-Bin YANG

Inventor： Wen-Bin YANG

IPC: G01N33/58 ,  C07H15/26

CPC classification number: G01N33/58 ,  C07H15/26 ,  G01N33/531 ,  Y10T436/14

Abstract: Novel method and reagents for generating reversibly tagged saccharides, aldehydes, carboxyl acids, or orthoacetates useful in analytical and diagnostic applications are disclosed. Saccharides are coupled at the reducing end to tagging moieties comprising a reagent selected from a ortho-diaminobenzoic(DAB)-peptide, an aldo-imidazole or N-methylated aldo-imidazole, or an ortho-phenyldiamine (OPD) or substituted OPD. The tagged saccharide further comprising detectable or functional groups coupled to the tagging moiety are provided. Kits and reagents for chromatography and mass spectrometry are disclosed.

Abstract translation: 公开了用于生成可用于分析和诊断应用的可逆标记的糖，醛，羧酸或原乙酸盐的新方法和试剂。 糖在还原端耦合到包含选自邻二氨基苯甲酸（DAB）肽，醛 - 咪唑或N-甲基化的醛 - 咪唑或邻苯基二胺（OPD）或取代的OPD的试剂的标记部分。 提供了进一步包含与标记部分偶联的可检测或官能团的标记糖。 公开了用于色谱和质谱的试剂盒和试剂。

公开(公告)号：US08404589B2

公开(公告)日：2013-03-26

申请号：US12754912

申请日：2010-04-06

Applicant: Andrew J. Kellock ,  Christian Lavoie ,  Ahmet Ozcan ,  Stephen Rossnagel ,  Bin Yang ,  Zhen Zhang ,  Yu Zhu ,  Stefan Zollner

Inventor： Andrew J. Kellock ,  Christian Lavoie ,  Ahmet Ozcan ,  Stephen Rossnagel ,  Bin Yang ,  Zhen Zhang ,  Yu Zhu ,  Stefan Zollner

IPC: H01L21/44

CPC classification number: H01L21/28518 ,  H01L29/66795 ,  H01L29/785 ,  H01L2029/7858 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A method for forming a silicide contact includes depositing a metal layer on silicon such that the metal layer intermixes with the silicon to form an intermixed region on the silicon; removing an unintermixed portion of the metal layer from the intermixed region; and annealing the intermixed region to form a silicide contact on the silicon. A semiconductor device comprising a silicide contact located over a silicon layer of the semiconductor device, the silicide contact comprising nickel (Ni) and silicon (Si) and having Ni amount equivalent to a thickness of about 21 angstroms or less.

Abstract translation: 形成硅化物接触的方法包括在硅上沉积金属层，使得金属层与硅混合以在硅上形成混合区; 从所述混合区域去除所述金属层的未混合部分; 并且对所述混合区进行退火以在所述硅上形成硅化物接触。 一种半导体器件，包括位于所述半导体器件的硅层上方的硅化物触点，所述硅化物触点包含镍（Ni）和硅（Si），并且具有相当于约21埃或更小的厚度的Ni量。

公开(公告)号：US08394691B2

公开(公告)日：2013-03-12

申请号：US12814346

申请日：2010-06-11

Applicant: Bin Yang ,  Man Fai Ng

Inventor： Bin Yang ,  Man Fai Ng

IPC: H01L21/8238

CPC classification number: H01L29/7848 ,  H01L29/045 ,  H01L29/165 ,  H01L29/6659 ,  H01L29/66636 ,  H01L29/7833

Abstract: Apparatus for semiconductor device structures and related fabrication methods are provided. One method for fabricating a semiconductor device structure involves forming a gate structure overlying a region of semiconductor material, wherein the width of the gate structure is aligned with a crystal direction of the semiconductor material. The method continues by forming recesses about the gate structure and forming a stress-inducing semiconductor material in the recesses.

Abstract translation: 提供了半导体器件结构和相关制造方法的装置。 制造半导体器件结构的一种方法包括形成覆盖半导体材料区域的栅极结构，其中栅极结构的宽度与半导体材料的<100>晶体方向对齐。 该方法通过在栅极结构周围形成凹槽并在凹部中形成应力诱导半导体材料来继续。