公开(公告)号：US20240136400A1

公开(公告)日：2024-04-25

申请号：US18405621

申请日：2024-01-05

Applicant: GLOBALFOUNDRIES U.S. Inc.

Inventor： Alexander Derrickson ,  Vibhor Jain ,  Judson R. Holt ,  Jagar Singh ,  Mankyu Yang

IPC: H01L29/08 ,  H01L29/06 ,  H01L29/10 ,  H01L29/417 ,  H01L29/735 ,  H01L29/737

CPC classification number: H01L29/0821 ,  H01L29/0649 ,  H01L29/0808 ,  H01L29/0817 ,  H01L29/1008 ,  H01L29/41708 ,  H01L29/735 ,  H01L29/737

Abstract: The present disclosure relates to semiconductor structures and, more particularly, to a lateral bipolar transistor with gated collector and methods of manufacture. The structure includes: an extrinsic base region vertically over a semiconductor substrate and comprising asymmetrical sidewall spacers on opposing sidewalls of the extrinsic base region; a collector region on the semiconductor substrate and separated from the extrinsic base region by at least a first spacer of the asymmetrical sidewall spacers; and an emitter region on the semiconductor substrate and separated from the extrinsic base region by a second spacer of the asymmetrical sidewall spacers.

公开(公告)号：US20240130255A1

公开(公告)日：2024-04-18

申请号：US18046170

申请日：2022-10-13

Applicant: GlobalFoundries U.S. Inc.

Inventor： Robert Viktor Seidel ,  Suk Hee Jang ,  Anastasia Voronova ,  Young Seon You

IPC: H01L45/00 ,  H01L27/24

CPC classification number: H01L45/1246 ,  H01L27/2463 ,  H01L45/08 ,  H01L45/1233 ,  H01L45/16

Abstract: The disclosure provides a structure and method for a memory element to confine a metal (e.g., a remaining portion of a metallic residue) with a spacer. A structure according to the disclosure includes a memory element over a first portion of an insulator layer. A portion of the memory element includes a sidewall over the insulator layer. A spacer is adjacent the sidewall of the memory element and on the first portion of the insulator layer. A metal-dielectric layer is within an interface between the spacer and the sidewall or an interface between the spacer and the first portion of the insulator layer. The insulator layer includes a second portion adjacent the first portion, and the second portion does not include the memory element, the spacer, and the metal-dielectric layer thereon.

公开(公告)号：US20240127868A1

公开(公告)日：2024-04-18

申请号：US18046961

申请日：2022-10-17

Applicant: GlobalFoundries U.S. Inc.

Inventor： Siva Kumar Chinthu ,  Suresh Pasupula ,  Devesh Dwivedi ,  Chunsung Chiang

IPC: G11C7/06 ,  G11C7/10 ,  G11C7/12

CPC classification number: G11C7/067 ,  G11C7/109 ,  G11C7/12

Abstract: Embodiments of the disclosure provide memory circuit, a sense amplifier and associated method for reading a resistive state in a memory device. The sense amplifier includes a bit cell configurable to a high or low resistance state; a sensing circuit that detects a voltage drop across the bit cell in response to an applied read current during a read operation and generates a high or low logic output at an output node; and a pulse generation circuit that increases the applied read current with an injected current pulse when a low to high transition of the resistive state of the bit cell is detected.

公开(公告)号：US20240120373A1

公开(公告)日：2024-04-11

申请号：US18045799

申请日：2022-10-11

Applicant: GlobalFoundries U.S. Inc.

Inventor： HONG YU ,  DAVID PRITCHARD

IPC: H01L29/06 ,  H01L29/10 ,  H01L29/40 ,  H01L29/423 ,  H01L29/66 ,  H01L29/808

CPC classification number: H01L29/0649 ,  H01L29/1066 ,  H01L29/401 ,  H01L29/42364 ,  H01L29/66893 ,  H01L29/808

Abstract: A semiconductor device is provided. The semiconductor device includes a substrate, a first gate electrode, a second gate electrode, and an isolation structure. The first gate electrode is over the substrate and the second gate electrode is laterally adjacent thereto. The isolation structure is in contact with the first gate electrode and the second gate electrode.

公开(公告)号：US20240119974A1

公开(公告)日：2024-04-11

申请号：US18045529

申请日：2022-10-11

Applicant: GlobalFoundries U.S. Inc.

Inventor： Venkatesh P. Gopinath ,  Pirooz Parvarandeh

IPC: G11C7/10 ,  G11C7/12 ,  G11C13/00

CPC classification number: G11C7/1039 ,  G11C7/1012 ,  G11C7/12 ,  G11C13/0069

Abstract: Disclosed structures include a partitioned memory architecture, which includes single resistor or dual resistor memory elements, which is configured for in-memory pipeline processing with minimal local IR drops, and which further includes additional circuitry to facilitate calibration processing. In some embodiments, the additional circuitry enables calibration processing when in-memory pipeline processing is paused. In these embodiments, the same bitlines and data sensing elements used for in-memory pipeline processing are also used for calibration processing. In other embodiments, the additional circuitry enables calibration processing concurrent with in-memory pipeline processing. In these embodiments, the additional circuitry includes duplicate pairs of memory elements with programmable resistors that can be connected to the operational circuitry for in-memory pipeline processing, to the calibration circuitry (including calibration-specific sense lines and sensing elements) for calibration processing, or to neither such that one memory element of the duplicate pair always remains operational allowing the other to undergo calibration.

公开(公告)号：US20240111088A1

公开(公告)日：2024-04-04

申请号：US17936939

申请日：2022-09-30

Applicant: GlobalFoundries U.S. Inc.

Inventor： Yusheng Bian ,  Ryan William Sporer

IPC: G02B6/12 ,  G02B6/13

CPC classification number: G02B6/12004 ,  G02B6/13 ,  G02B2006/12061

Abstract: A structure or PIC structure includes a hybrid plasmonic (HP) waveguide. The HP waveguide includes a waveguide core, and a metal silicide layer contacting the waveguide core. The metal silicide layer replaces noble metals typically provided in hybrid plasmonic waveguides, providing improved optical signal containment characteristics. The metal silicide layer is also compatible with CMOS fabrication techniques, and capable of additional scaling with other CMOS structures. The HP waveguide also has a reduce form factor compared to conventional HP waveguides, providing room for more waveguides closer together.

公开(公告)号：US20240105683A1

公开(公告)日：2024-03-28

申请号：US17955225

申请日：2022-09-28

Applicant: GlobalFoundries U.S. Inc.

Inventor： Vvss Satyasuresh Choppalli ,  Anupam Dutta ,  Rajendran Krishnasamy ,  Robert Gauthier, JR. ,  Xiang Xiang Lu ,  Anindya Nath

IPC: H01L25/07 ,  H01L21/77 ,  H01L23/14 ,  H01L23/522

CPC classification number: H01L25/072 ,  H01L21/77 ,  H01L23/147 ,  H01L23/5228

Abstract: Structures including multiple semiconductor devices and methods of forming same. The structure comprises a first device structure including a first well and a second well in a semiconductor substrate, a second device structure including a doped region in the semiconductor substrate, and a first high-resistivity region in the semiconductor substrate. The first well has a first conductivity type, the second well has a second conductivity type opposite to the first conductivity type, and the first well adjoins the second well to define a p-n junction. The doped region of the second device structure has the first conductivity type or the second conductivity type. The high-resistivity region has a higher electrical resistivity than the semiconductor substrate, and the high-resistivity region is positioned between the first device structure and the second device structure.

公开(公告)号：US20240103217A1

公开(公告)日：2024-03-28

申请号：US17953804

申请日：2022-09-27

Applicant: GlobalFoundries U.S. Inc.

Inventor： Brian McGowan ,  Ping-Chuan Wang ,  Oscar Restrepo

IPC: G02B6/122

CPC classification number: G02B6/122 ,  G02B2006/12142

Abstract: Structures for a thermo-optic phase shifter and methods of forming such structures. The structure comprises a waveguide structure including a waveguide core. The structure further comprises a silicide layer, a first dielectric layer arranged in a lateral direction between the silicide layer and the waveguide core, and a second dielectric layer positioned over the waveguide core, the silicide layer, and the first dielectric layer. The first dielectric layer comprises a first material having a first thermal conductivity, and the second dielectric layer comprises a second material having a second thermal conductivity that is less than the first thermal conductivity.

公开(公告)号：US20240097029A1

公开(公告)日：2024-03-21

申请号：US17933304

申请日：2022-09-19

Applicant: GlobalFoundries U.S. Inc.

Inventor： Nan Wu

IPC: H01L29/78 ,  H01L21/225 ,  H01L21/285 ,  H01L21/74 ,  H01L29/10 ,  H01L29/40 ,  H01L29/423 ,  H01L29/45 ,  H01L29/66

CPC classification number: H01L29/7831 ,  H01L21/2252 ,  H01L21/28518 ,  H01L21/743 ,  H01L29/1083 ,  H01L29/1087 ,  H01L29/401 ,  H01L29/42376 ,  H01L29/45 ,  H01L29/66484 ,  H01L29/6656

Abstract: Disclosed is a structure including a field effect transistor (FET). The FET includes, on an insulator layer above a substrate, source/drain regions and a section of a semiconductor layer extending laterally between the source/drain regions. A primary gate structure is made of the insulator layer and a well region in the substrate opposite at least the section of the semiconductor layer extending laterally between the source/drain regions. One or two secondary gate structures are on the semiconductor layer between and near one or both of the source/drain regions, respectively. The FET can further include a patterned conformal dielectric layer, which is on the center of the semiconductor layer between the source/drain regions, and which extends onto the secondary gate structure(s). Also disclosed are methods of operating the structure by biasing the secondary gate structure(s) to adjust the effective gate length of the FET and methods of forming the structure.

公开(公告)号：US11935928B2

公开(公告)日：2024-03-19

申请号：US17747476

申请日：2022-05-18

Applicant: GLOBALFOUNDRIES U.S. Inc.

Inventor： Hong Yu ,  Jianwei Peng ,  Vibhor Jain

IPC: H01L29/417 ,  H01L29/08 ,  H01L29/10 ,  H01L29/423 ,  H01L29/66 ,  H01L29/737

CPC classification number: H01L29/41708 ,  H01L29/0804 ,  H01L29/0821 ,  H01L29/1008 ,  H01L29/42304 ,  H01L29/66242 ,  H01L29/7371

Abstract: The present disclosure relates to semiconductor structures and, more particularly, to a bipolar transistor with self-aligned asymmetric spacer and methods of manufacture. The structure includes: a base formed on a semiconductor substrate; an asymmetrical spacer surrounding the base; an emitter on a first side of the base and separated from the base by the asymmetrical spacer; and a collector on a second side of the base and separated from the base by the asymmetrical spacer.