公开(公告)号：US20060261409A1

公开(公告)日：2006-11-23

申请号：US11341519

申请日：2006-01-30

Applicant: Hans Cho ,  Takashi Noguchi ,  Wenxu Xianyu ,  Do-Young Kim ,  Huaxiang Yin ,  Xiaoxin Zhang

Inventor： Hans Cho ,  Takashi Noguchi ,  Wenxu Xianyu ,  Do-Young Kim ,  Huaxiang Yin ,  Xiaoxin Zhang

IPC: H01L27/12

CPC classification number: H01L29/78654 ,  H01L29/0673 ,  H01L29/66772 ,  H01L29/78696 ,  Y10S977/762 ,  Y10S977/814 ,  Y10S977/90 ,  Y10S977/938 ,  Y10T428/26

Abstract: A silicon nanowire substrate having a structure in which a silicon nanowire film having a fine line-width is formed on a substrate, a method of manufacturing the same, and a method of manufacturing a thin film transistor using the same. The method of manufacturing the silicon nanowire substrate includes preparing a substrate, forming an insulating film on the substrate, forming a silicon film on the insulating film, patterning the insulating film and the silicon film into a strip shape, reducing the line-width of the insulating film by undercut etching at least one lateral side of the insulating film, and forming a self-aligned silicon nanowire film on an upper surface of the insulating film by melting and crystallizing the silicon film.

Abstract translation: 具有其中在衬底上形成具有细线宽度的硅纳米线膜的结构的硅纳米线衬底，其制造方法以及使用其制造薄膜晶体管的方法。 制造硅纳米线基板的方法包括：准备基板，在基板上形成绝缘膜，在绝缘膜上形成硅膜，将绝缘膜和硅膜图形化成带状，减小线宽 通过对绝缘膜的至少一个侧面进行底切蚀刻来绝缘膜，并且通过使硅膜熔化和结晶，在绝缘膜的上表面上形成自对准硅纳米线膜。

公开(公告)号：US20060145158A1

公开(公告)日：2006-07-06

申请号：US11322235

申请日：2006-01-03

Applicant: Takashi Noguchi ,  Huaxiang Yin ,  Ji-sim Jung ,  Wenxu Xianyu ,  Jang-yeon Kwon ,  Yong-han Roh ,  Suk-won Jeong ,  Seong-hoon Jeong

Inventor： Takashi Noguchi ,  Huaxiang Yin ,  Ji-sim Jung ,  Wenxu Xianyu ,  Jang-yeon Kwon ,  Yong-han Roh ,  Suk-won Jeong ,  Seong-hoon Jeong

IPC: H01L29/76

CPC classification number: H01L29/66757 ,  H01L29/4908

Abstract: Provided is a silicon thin film transistor (TFT) including: a substrate; a silicon channel layer formed on the substrate with a source and a drain on both sides thereof; a gate insulating layer formed on the silicon channel layer; and a gate formed on the gate insulating layer, wherein the gate insulating layer has a structure including an HfOx film. The TFT has a low leakage current.

Abstract translation: 提供一种硅薄膜晶体管（TFT），包括：基板; 形成在所述基板上的硅沟道层，其两侧具有源极和漏极; 形成在硅沟道层上的栅极绝缘层; 以及形成在所述栅极绝缘层上的栅极，其中所述栅极绝缘层具有包括HfO x膜的结构。 TFT具有低漏电流。

公开(公告)号：US20060121691A1

公开(公告)日：2006-06-08

申请号：US11071175

申请日：2005-03-04

Applicant: Takashi Noguchi ,  Wenxu Xianyu ,  Huaxiang Yin

Inventor： Takashi Noguchi ,  Wenxu Xianyu ,  Huaxiang Yin

IPC: H01L21/30

CPC classification number: H01L21/76254

Abstract: Provided is a method of manufacturing a single crystal Si film. The method includes: preparing a Si substrate on which a first oxide layer is formed and an insulating substrate on which a second oxide layer is formed; forming a dividing layer at a predetermined depth from a surface of the Si substrate by implanting hydrogen ions from above the first oxide layer; bonding the insulating substrate to the Si substrate so that the first oxide layer contacts the second oxide layer; and forming a single crystal Si film having a predetermined thickness on the insulating substrate by cutting the dividing layer by irradiating a laser beam from above the insulating substrate. Therefore, a single crystal Si film having a predetermined thickness can be formed on an insulating substrate.

公开(公告)号：US20060084204A1

公开(公告)日：2006-04-20

申请号：US11199272

申请日：2005-08-09

Applicant: Huaxiang Yin ,  Wenxu Xianyu ,  Takashi Noguchi ,  Hans Cho ,  Ji-sim Jung

Inventor： Huaxiang Yin ,  Wenxu Xianyu ,  Takashi Noguchi ,  Hans Cho ,  Ji-sim Jung

IPC: H01L21/84

CPC classification number: H01L21/02675 ,  H01L21/2026 ,  H01L21/84 ,  H01L27/1203 ,  H01L29/66795 ,  H01L29/785

Abstract: A method of manufacturing a thin film transistor is provided. The method includes forming an amorphous silicon layer on a substrate, forming a source region, a drain region, and a region of a plurality of channels electrically interposed between the source region and the drain region by patterning the amorphous silicon layer, annealing a region of the channels, sequentially forming a gate oxide film and a gate electrode on a channel surface, and doping the source region and the drain region.

公开(公告)号：US09691878B2

公开(公告)日：2017-06-27

申请号：US14436892

申请日：2012-10-30

Applicant: Haizhou Yin ,  Huilong Zhu ,  Changliang Qin ,  Huaxiang Yin

Inventor： Haizhou Yin ,  Huilong Zhu ,  Changliang Qin ,  Huaxiang Yin

IPC: H01L29/06 ,  H01L29/66 ,  H01L29/78 ,  H01L29/165 ,  H01L21/762 ,  H01L21/02 ,  H01L21/265 ,  H01L21/306 ,  H01L21/308 ,  H01L29/161

CPC classification number: H01L29/66636 ,  H01L21/02381 ,  H01L21/02529 ,  H01L21/02532 ,  H01L21/26513 ,  H01L21/30604 ,  H01L21/3081 ,  H01L21/3083 ,  H01L21/76224 ,  H01L29/0653 ,  H01L29/161 ,  H01L29/165 ,  H01L29/665 ,  H01L29/6656 ,  H01L29/7848

Abstract: Provided is a method for manufacturing a MOSFET, including: forming a shallow trench isolation (STI) in a semiconductor substrate to define an active region for the MOSFET; performing etching with the STI as a mask, to expose a surface of the semiconductor substrate, and to protrude a portion of the STI with respect to the surface of the semiconductor substrate, resulting in a protruding portion; forming a first spacer on sidewalls of the protruding portion; forming a gate stack on the semiconductor substrate; forming a second spacer surrounding the gate stack; forming openings in the semiconductor substrate with the STI, the gate stack, the first spacer and the second spacer as a mask; epitaxially growing a semiconductor layer with a bottom surface and sidewalls of each of the openings as a growth seed layer; and performing ion implantation into the semiconductor layer to form source and drain regions.

公开(公告)号：US20160233317A1

公开(公告)日：2016-08-11

申请号：US14387830

申请日：2013-08-06

Applicant: Huaxiang YIN ,  Xiaolong MA ,  Weijia XU ,  Qiuxia XU ,  Huilong ZHU

Inventor： Huaxiang YIN ,  Xiaolong MA ,  Weijia XU ,  Qiuxia XU ,  Huilong ZHU

IPC: H01L29/66 ,  H01L29/423 ,  H01L29/06

CPC classification number: H01L29/66795 ,  H01L29/0673 ,  H01L29/42384 ,  H01L29/66439 ,  H01L29/78696

Abstract: A MOS transistor with stacked nanowires and a method of manufacturing the same. The transistor may include a stack of cascaded nanowires extending in a first direction on a substrate; a gate stack extending in a second direction across the nanowire stack; source and drain regions disposed on opposite sides of the gate stack in the second direction; and a channel region constituted of the nanowire stack between the source and drain regions. he cascaded nanowires can be formed by repeated operations of etching back, and lateral etching and then filling of grooves, thereby increasing an effective width of the channel, increasing a total area of an effective conductive section, and thus improving a drive current.

Abstract translation: 具有堆叠的纳米线的MOS晶体管及其制造方法。 晶体管可以包括在衬底上沿第一方向延伸的级联纳米线的叠层; 沿着第二方向跨越纳米线堆叠延伸的栅极堆叠; 源极和漏极区域，设置在栅极堆叠的第二方向的相对侧上; 以及由源区和漏区之间的纳米线叠层构成的沟道区。 他级联的纳米线可以通过反复的蚀刻操作形成，横向蚀刻然后填充槽，从而增加通道的有效宽度，增加有效导电部分的总面积，从而提高驱动电流。

公开(公告)号：US08889519B2

公开(公告)日：2014-11-18

申请号：US13812499

申请日：2012-10-12

Applicant: Xiaolong Ma ,  Huaxiang Yin ,  Zuozhen Fu

Inventor： Xiaolong Ma ,  Huaxiang Yin ,  Zuozhen Fu

IPC: H01L21/336 ,  H01L29/66 ,  H01L29/78 ,  H01L29/161 ,  H01L21/02 ,  H01L21/265 ,  H01L29/10 ,  H01L29/165 ,  H01L21/268 ,  H01L29/51

CPC classification number: H01L29/66477 ,  H01L21/02381 ,  H01L21/0245 ,  H01L21/02452 ,  H01L21/02532 ,  H01L21/02535 ,  H01L21/02675 ,  H01L21/26506 ,  H01L21/268 ,  H01L29/1054 ,  H01L29/161 ,  H01L29/165 ,  H01L29/517 ,  H01L29/665 ,  H01L29/66575 ,  H01L29/66651 ,  H01L29/66659 ,  H01L29/78 ,  H01L29/7848

Abstract: The present invention discloses a semiconductor device, comprising: a substrate, a gate stack structure on the substrate, source and drain regions in the substrate on both sides of the gate stack structure, and a channel region between the source and drain regions in the substrate, characterized in that at least one of the source and drain regions comprises a GeSn alloy. In accordance with the semiconductor device and method for manufacturing the same of the present invention, GeSn stressed source and drain regions with high concentration of Sn is formed by implanting precursors and performing a laser rapid annealing, thus the device carrier mobility of the channel region is effectively enhanced and the device drive capability is further improved.

Abstract translation: 本发明公开了一种半导体器件，包括：衬底，衬底上的栅极堆叠结构，栅极堆叠结构两侧的衬底中的源极和漏极区域以及衬底中的源极和漏极区域之间的沟道区域 其特征在于源区和漏区中的至少一个包括GeSn合金。 根据本发明的半导体器件及其制造方法，通过注入前体并进行激光快速退火形成GeSn应力的高浓度Sn的源区和漏极区，因此沟道区的器件载流子迁移率为 有效提高了设备​​驱动能力。

公开(公告)号：US08853024B2

公开(公告)日：2014-10-07

申请号：US13812498

申请日：2012-08-27

Applicant: Huaxiang Yin ,  Jiang Yan ,  Dapeng Chen

Inventor： Huaxiang Yin ,  Jiang Yan ,  Dapeng Chen

IPC: H01L21/8238

CPC classification number: H01L27/088 ,  H01L21/82345 ,  H01L21/823842 ,  H01L27/092 ,  H01L29/4966 ,  H01L29/517 ,  H01L29/66545 ,  H01L29/66666 ,  H01L29/7848

Abstract: The present invention discloses a method for manufacturing a semiconductor device comprising the steps of: forming a plurality of source and drain regions in a substrate; forming a plurality of gate spacer structures and an interlayer dielectric layer around the gate spacer structures on the substrate, wherein the gate spacer structures enclose a plurality of first gate trenches and a plurality of second gate trenches; sequentially depositing a first gate insulating layer and a second gate insulating layer, a first blocking layer and a second work function regulating layer in the first and second gate trenches; performing selective etching to remove the second work function regulating layer from the first gate trenches to expose the first blocking layer; depositing a first work function regulating layer on the first blocking layer in the first gate trenches and on the second work function regulating layer in the second gate trenches; and depositing a resistance regulating layer on the first work function regulating layer in the first gate trenches and on the first work function regulating layer in the second gate trench.

Abstract translation: 本发明公开了一种制造半导体器件的方法，包括以下步骤：在衬底中形成多个源极和漏极区; 在所述衬底上的所述栅极隔离物结构周围形成多个栅极间隔物结构和层间电介质层，其中所述栅极间隔物结构包围多个第一栅极沟槽和多个第二栅极沟槽; 在第一和第二栅极沟槽中依次沉积第一栅极绝缘层和第二栅极绝缘层，第一阻挡层和第二功函数调节层; 执行选择性蚀刻以从第一栅极沟槽去除第二功函数调节层以暴露第一阻挡层; 在第一栅极沟槽中的第一阻挡层上和第二栅极沟槽中的第二功函数调节层上沉积第一功函数调节层; 以及在第一栅极沟槽中的第一功函数调节层和第二栅沟中的第一功函数调节层上沉积电阻调节层。

公开(公告)号：US08841190B2

公开(公告)日：2014-09-23

申请号：US13519884

申请日：2012-04-10

Applicant: Changliang Qin ,  Huaxiang Yin

Inventor： Changliang Qin ,  Huaxiang Yin

IPC: H01L29/872

CPC classification number: H01L21/823807 ,  H01L21/823814 ,  H01L29/045 ,  H01L29/165 ,  H01L29/66636 ,  H01L29/7848

Abstract: This invention relates to a MOS device for making the source/drain region closer to the channel region and a method of manufacturing the same, comprising: providing an initial structure, which includes a substrate, an active region, and a gate stack; performing ion implantation in the active region on both sides of the gate stack, such that part of the substrate material undergoes pre-amorphization to form an amorphous material layer; forming a first spacer; with the first spacer as a mask, performing dry etching, thereby forming a recess, with the amorphous material layer below the first spacer kept; performing wet etching using an etchant solution that is isotropic to the amorphous material layer and whose etch rate to the amorphous material layer is greater than or substantially equal to the etch rate to the {100} and {110} surfaces of the substrate material but is far greater than the etch rate to the {111} surface of the substrate material, thus removing the amorphous material layer below the first spacer, such that the substrate material below the amorphous material layer is exposed to the solution and is etched thereby, and in the end, forming a Sigma shaped recess that extends to the nearby region below the gate stack; and epitaxially forming SiGe in the Sigma shaped recess.

Abstract translation: 本发明涉及一种用于使源极/漏极区域更靠近沟道区域的MOS器件及其制造方法，包括：提供包括衬底，有源区域和栅极堆叠的初始结构; 在栅极堆叠的两侧上的有源区中进行离子注入，使得衬底材料的一部分经历预非晶化以形成无定形材料层; 形成第一间隔物; 以第一间隔物作为掩模，进行干蚀刻，从而形成凹部，保持第一间隔物下面的非晶材料层; 使用对非晶材料层各向同性的蚀刻剂溶液进行湿蚀刻，并且其对非晶材料层的蚀刻速率大于或基本上等于对基板材料的{100}和{110}表面的蚀刻速率，但是 远远大于衬底材料的{111}表面的蚀刻速率，从而去除第一间隔物下方的无定形材料层，使得无定形材料层下面的衬底材料暴露于溶液并被蚀刻，并且在 结束，形成延伸到栅堆叠下方的附近区域的Sigma形凹部; 并在Sigma形凹部中外延形成SiGe。

公开(公告)号：US08828881B2

公开(公告)日：2014-09-09

申请号：US13381005

申请日：2011-08-10

Applicant: Lingkkuan Meng ,  Huaxiang Yin

Inventor： Lingkkuan Meng ,  Huaxiang Yin

IPC: H01L21/3065 ,  H01L21/3105 ,  H01L21/768 ,  H01L29/78

CPC classification number: H01L21/31055 ,  H01L21/76801 ,  H01L29/78

Abstract: The invention discloses an etch-back method for planarization at the position-near-interface of an interlayer dielectric (ILD), comprising: depositing or growing a thick layer of SiO2 by the chemical vapor deposition or oxidation method on a surface of a wafer; spin-coating a layer of SOG and then performing a heat treatment to obtain a relatively uniform stack structure; perform an etch-back on the SOG using a plasma etching, and stopping when approaching the position-near-interface of SiO2; performing a plasma etch-back on the remaining SOG/SiO2 structure at the position-near-interface until achieving a desired thickness. Since a two-step etching at the position-near-interface is employed, an extremely good smooth surface of the ILD is obtained. That is, a planar and tidy surface of the ILD is obtained not only in the center region, but also even at the edge of the wafer.

Abstract translation: 本发明公开了一种用于在层间电介质（ILD）的位置 - 接近界​​面处的平坦化的回蚀刻方法，包括：通过化学气相沉积或氧化方法在晶片的表面上沉积或生长厚SiO 2层; 旋涂一层SOG，然后进行热处理以获得相对均匀的堆叠结构; 使用等离子体蚀刻对SOG进行回蚀，并且在接近SiO 2的位置 - 接近界​​面时停止; 在靠近界面的位置处对剩余的SOG / SiO 2结构进行等离子体回蚀，直到达到期望的厚度。 由于在位置 - 接近界​​面处进行两步蚀刻，因此获得了非常好的ILD平滑表面。 也就是说，ILD的平面和整洁的表面不仅在中心区域中获得，而且在晶片的边缘处获得。