公开(公告)号：US07821809B2

公开(公告)日：2010-10-26

申请号：US11267825

申请日：2005-11-07

Applicant: In-Kyeong Yoo ,  Myoung-Jae Lee ,  Sun-Ae Seo ,  David Seo

Inventor： In-Kyeong Yoo ,  Myoung-Jae Lee ,  Sun-Ae Seo ,  David Seo

IPC: G11C11/00

CPC classification number: H01L27/24 ,  G11C13/0004 ,  G11C13/0007 ,  G11C13/003 ,  G11C2213/31 ,  G11C2213/32 ,  G11C2213/75

Abstract: A nonvolatile memory device including one resistor and one transistor. The resistor may correspond to a resistance layer electrically connected to a first impurity region and a second impurity region of the transistor.

Abstract translation: 一种非易失性存储器件，包括一个电阻器和一个晶体管。 电阻器可以对应于电连接到晶体管的第一杂质区域和第二杂质区域的电阻层。

公开(公告)号：US20080257861A1

公开(公告)日：2008-10-23

申请号：US11882112

申请日：2007-07-30

Applicant: In-kyeong Yoo ,  Soo-hwan Jeong ,  Sun-ae Seo ,  In-sook Kim

Inventor： In-kyeong Yoo ,  Soo-hwan Jeong ,  Sun-ae Seo ,  In-sook Kim

IPC: B44C1/22

CPC classification number: B82B3/00 ,  B29C59/022 ,  B29C59/026 ,  B29C2059/023 ,  B82Y10/00 ,  B82Y30/00 ,  B82Y40/00 ,  H01L21/32139

Abstract: A method of manufacturing a nanochannel-array and a method of fabricating a nanodot using the nanochannel-array are provided. The nanochannel-array manufacturing method includes: performing first anodizing to form a first alumina layer having a channel array formed by a plurality of cavities on an aluminum substrate; etching the first alumina layer to a predetermined depth and forming a plurality of concave portions on the aluminum substrate, wherein each concave portion corresponds to the bottom of each channel of the first alumina layer; and performing second anodizing to form a second alumina layer having an array of a plurality of channels corresponding to the plurality of concave portions on the aluminum substrate. The array manufacturing method makes it possible to obtain finely ordered cavities and form nanoscale dots using the cavities.

Abstract translation: 提供一种制造纳米通道阵列的方法和使用纳米通道阵列制造纳米点的方法。 纳米通道阵列制造方法包括：执行第一阳极氧化以形成具有由铝基板上的多个空腔形成的沟道阵列的第一氧化铝层; 将第一氧化铝层蚀刻到预定深度并在铝基板上形成多个凹部，其中每个凹部对应于第一氧化铝层的每个通道的底部; 以及进行第二阳极氧化以形成具有与所述铝基板上的所述多个凹部对应的多个通道的阵列的第二氧化铝层。 阵列制造方法使得可以使用空腔获得精细排列的空腔并形成纳米级点。

公开(公告)号：US07439566B2

公开(公告)日：2008-10-21

申请号：US11485340

申请日：2006-07-13

Applicant: Jae-Woong Hyun ,  In-Kyeong Yoo ,  Yoon-Dong Park ,  Choong-Rae Cho ,  Sung-Il Cho

Inventor： Jae-Woong Hyun ,  In-Kyeong Yoo ,  Yoon-Dong Park ,  Choong-Rae Cho ,  Sung-Il Cho

IPC: H01L29/06

CPC classification number: H01L27/108 ,  H01L27/101 ,  H01L27/2436 ,  H01L45/146

Abstract: A semiconductor memory device may have a lower leakage current and/or higher reliability, e.g., a longer retention time and/or a shorter refresh time. The device may include a switching device and a capacitor. A source of the switching device may be connected to a first end of a metal-insulator transition film resistor, and at least one electrode of the capacitor may be connected to a second end of the metal-insulator transition film resistor. The metal-insulator transition film resistor may transition between an insulator and a conductor according to a voltage supplied to the first and second ends thereof.

Abstract translation: 半导体存储器件可以具有较低的漏电流和/或更高的可靠性，例如较长的保留时间和/或更短的刷新时间。 该装置可以包括开关装置和电容器。 开关器件的源极可以连接到金属 - 绝缘体转变膜电阻器的第一端，并且电容器的至少一个电极可以连接到金属 - 绝缘体转变膜电阻器的第二端。 金属 - 绝缘体转变膜电阻器可以根据提供给其第一和第二端的电压在绝缘体和导体之间转变。

公开(公告)号：US07414295B2

公开(公告)日：2008-08-19

申请号：US11274475

申请日：2005-11-16

Applicant: Choong-Rae Cho ,  In-Kyeong Yoo ,  Myoung-Jae Lee

Inventor： Choong-Rae Cho ,  In-Kyeong Yoo ,  Myoung-Jae Lee

IPC: H01L29/8605 ,  G11C11/00

CPC classification number: H01L29/685

Abstract: A transistor in which a physical property of its channel is changed according to an applied voltage, and methods of manufacturing and operating the same are provided. The transistor may include a first conductive layer on a substrate, a phase change layer and a second conductive layer which are sequentially stacked on the first conductive layer, a first current direction limiting unit and a second current direction limiting unit formed on the second conductive layer by being separated within a space, a third conductive layer and a fourth conductive layer formed on the first current direction limiting unit and the second current direction limiting unit, respectively, a word line connected to the third conductive layer, a bit line connected to the fourth conductive layer, and a voltage lowering unit connected to the word line.

Abstract translation: 提供其通道的物理特性根据施加的电压而改变的晶体管，并且提供其制造和操作方法。 晶体管可以包括基板上的第一导电层，相继层叠在第一导电层上的相变层和第二导电层，形成在第二导电层上的第一电流方向限制单元和第二电流方向限制单元 通过在空间内分离，分别形成在第一电流方向限制单元和第二电流方向限制单元上的第三导电层和第四导电层，连接到第三导电层的字线，连接到第三导电层的位线 第四导电层和连接到字线的降压单元。

公开(公告)号：US20070120580A1

公开(公告)日：2007-05-31

申请号：US11403902

申请日：2006-04-14

Applicant: Dong Kim ,  In-kyeong Yoo ,  Myoung-jae Lee ,  Sun-ae Seo ,  In-gyu Baek ,  Seung-eon Ahn ,  Byoung-ho Park ,  Young-kwan Cha ,  Sang-jin Park

Inventor： Dong Kim ,  In-kyeong Yoo ,  Myoung-jae Lee ,  Sun-ae Seo ,  In-gyu Baek ,  Seung-eon Ahn ,  Byoung-ho Park ,  Young-kwan Cha ,  Sang-jin Park

IPC: H03K19/00

CPC classification number: H01L45/04 ,  H01L27/2436 ,  H01L45/1233 ,  H01L45/1253 ,  H01L45/146

Abstract: A memory device may include a switching device and a storage node coupled with the switching device. The storage node may include a first electrode, a second electrode, a data storage layer and at least one contact layer. The data storage layer may be disposed between the first electrode and the second electrode and may include a transition metal oxide or aluminum oxide. The at least one contact layer may be disposed at least one of above or below the data storage layer and may include a conductive metal oxide.

Abstract translation: 存储器件可以包括与开关器件耦合的开关器件和存储节点。 存储节点可以包括第一电极，第二电极，数据存储层和至少一个接触层。 数据存储层可以设置在第一电极和第二电极之间，并且可以包括过渡金属氧化物或氧化铝。 至少一个接触层可以设置在数据存储层的上方或下方的至少一个上，并且可以包括导电金属氧化物。

公开(公告)号：US20070052001A1

公开(公告)日：2007-03-08

申请号：US11502426

申请日：2006-08-11

Applicant: Seung-eon Ahn ,  Jung-bin Yun ,  In-kyeong Yoo ,  Dong-chul Kim ,  Tae-hoon Kim

Inventor： Seung-eon Ahn ,  Jung-bin Yun ,  In-kyeong Yoo ,  Dong-chul Kim ,  Tae-hoon Kim

IPC: H01L29/76

CPC classification number: H01L45/04 ,  H01L27/2436 ,  H01L45/1233 ,  H01L45/146 ,  H01L45/1641

Abstract: A nonvolatile semiconductor memory device and a method of fabricating the same are provided. The nonvolatile memory device may include a switching device and a storage node connected to the switching device. The storage node may comprise a lower electrode, a data storing layer, and an upper electrode. The data storing layer may include a first region where a current path is formed at a first voltage, and a second region surrounding the first region where a current path is formed at a second voltage, greater than the first voltage. The first region may be positioned to contact the upper electrode and the lower electrode.

Abstract translation: 提供一种非易失性半导体存储器件及其制造方法。 非易失性存储器件可以包括连接到开关器件的开关器件和存储节点。 存储节点可以包括下电极，数据存储层和上电极。 数据存储层可以包括在第一电压处形成电流路径的第一区域和围绕第一区域的第二区域，其中电流路径形成在大于第一电压的第二电压处。 第一区域可以被定位成接触上电极和下电极。

公开(公告)号：US20060252276A1

公开(公告)日：2006-11-09

申请号：US11352310

申请日：2006-02-13

Applicant: Won-bong Choi ,  In-kyeong Yoo ,  Jae-uk Chu

Inventor： Won-bong Choi ,  In-kyeong Yoo ,  Jae-uk Chu

IPC: H01L21/31

CPC classification number: B82Y10/00 ,  G11C13/025 ,  G11C2213/17 ,  Y10S977/943

Abstract: A fast, reliable, highly integrated memory device formed of a carbon nanotube memory device and a method for forming the same, in which the carbon nanotube memory device includes a substrate, a source electrode, a drain electrode, a carbon nanotube having high electrical and thermal conductivity, a memory cell having excellent charge storage capability, and a gate electrode. The source electrode and drain electrode are arranged with a predetermined interval between them on the substrate and are subjected to a voltage. The carbon nanotube connects the source electrode to the drain electrode and serves as a channel for charge movement. The memory cell is located over the carbon nanotube and stores charges from the carbon nanotube. The gate electrode is formed in contact with the upper surface of the memory cell and controls the amount of charge flowing from the carbon nanotube into the memory cell.

Abstract translation: 一种由碳纳米管存储器件及其形成方法形成的快速，可靠，高度集成的存储器件，其中碳纳米管存储器件包括衬底，源电极，漏电极，具有高电的碳纳米管和 热导率，具有优异电荷存储能力的存储单元和栅电极。 源电极和漏电极在它们之间以预定间隔布置在衬底上并经受电压。 碳纳米管将源电极连接到漏电极并用作电荷运动的通道。 存储单元位于碳纳米管之上，并存储来自碳纳米管的电荷。 栅电极形成为与存储单元的上表面接触，并控制从碳纳米管流入存储单元的电荷量。

公开(公告)号：US07115306B2

公开(公告)日：2006-10-03

申请号：US11036379

申请日：2005-01-18

Applicant: Soo-hwan Jeong ,  Wan-jun Park ,  In-kyeong Yoo ,  Ju-hye Ko

Inventor： Soo-hwan Jeong ,  Wan-jun Park ,  In-kyeong Yoo ,  Ju-hye Ko

IPC: H05H1/24

CPC classification number: C30B29/602 ,  B82Y30/00 ,  B82Y40/00 ,  C01B32/162 ,  C23C26/00 ,  C30B25/00 ,  H01J1/304 ,  H01J9/025 ,  H01J2201/30469

Abstract: Provided are a method of growing carbon nanotubes and a carbon nanotube device. The method includes: depositing an aluminum layer on a substrate; forming an insulating layer over the substrate to cover the aluminum layer; patterning the insulating layer and the aluminum layer on the substrate to expose a side of the aluminum layer; forming a plurality of holes in the exposed side of the aluminum layer to a predetermined depth; depositing a catalyst metal layer on the bottoms of the holes; and growing the carbon nanotubes from the catalyst metal layer.

Abstract translation: 提供生长碳纳米管和碳纳米管装置的方法。 该方法包括：在基底上沉积铝层; 在所述基板上形成绝缘层以覆盖所述铝层; 将绝缘层和铝层图案化在基板上以暴露铝层的一侧; 在铝层的暴露侧形成多个孔至预定深度; 在所述孔的底部沉积催化剂金属层; 并从催化剂金属层生长碳纳米管。

公开(公告)号：US20060108639A1

公开(公告)日：2006-05-25

申请号：US11274475

申请日：2005-11-16

Applicant: Choong-Rae Cho ,  In-Kyeong Yoo ,  Myoung-Jae Lee

Inventor： Choong-Rae Cho ,  In-Kyeong Yoo ,  Myoung-Jae Lee

IPC: H01L29/94 ,  H01L29/76

CPC classification number: H01L29/685

Abstract: A transistor in which a physical property of its channel is changed according to an applied voltage, and methods of manufacturing and operating the same are provided. The transistor may include a first conductive layer on a substrate, a phase change layer and a second conductive layer which are sequentially stacked on the first conductive layer, a first current direction limiting unit and a second current direction limiting unit formed on the second conductive layer by being separated within a space, a third conductive layer and a fourth conductive layer formed on the first current direction limiting unit and the second current direction limiting unit, respectively, a word line connected to the third conductive layer, a bit line connected to the fourth conductive layer, and a voltage lowering unit connected to the word line.

公开(公告)号：US07009868B2

公开(公告)日：2006-03-07

申请号：US10995116

申请日：2004-11-24

Applicant: In-kyeong Yoo ,  Sun-ae Seo ,  Hyun-jo Kim

Inventor： In-kyeong Yoo ,  Sun-ae Seo ,  Hyun-jo Kim

IPC: G11C11/00

CPC classification number: H01L27/11206 ,  G11C16/0475 ,  H01L27/112

Abstract: A memory device having one transistor and one resistant element as a storing means and a method for driving the memory device, includes an NPN-type transistor formed on a semiconductor substrate, an interlayer insulating film formed on the semiconductor substrate to cover the transistor in which a contact hole exposing a source region of the transistor is formed, a resistant material in which a bit data “0” or “1” is written connected to the source region of the transistor by a conductive plug or an insulating film, and a conductive plate contacting the resistant material. The memory device exhibits improved degree of integration, reduced current consumption by lengthening a refresh period thereof, and enjoys simplified manufacturing process due to a simple memory cell structure.

Abstract translation: 具有一个晶体管和一个电阻元件作为存储装置的存储器件和用于驱动存储器件的方法包括形成在半导体衬底上的NPN型晶体管，形成在半导体衬底上以覆盖晶体管的层间绝缘膜， 形成暴露晶体管的源极区域的接触孔，通过导电插塞或绝缘膜将位数据“0”或“1”写入的电阻材料连接到晶体管的源极区域，并且导电 板接触抵抗材料。 存储器件通过延长其刷新周期而呈现出提高的集成度，降低的电流消耗，并且由于简单的存储单元结构而享有简化的制造工艺。