公开(公告)号：US07554140B2

公开(公告)日：2009-06-30

申请号：US11651892

申请日：2007-01-10

Applicant: Hoo-Sung Cho ,  Soon-Moon Jung ,  Won-Seok Cho ,  Jong-Hyuk Kim ,  Jae-Hun Jeong ,  Jae-Hoon Jang

Inventor： Hoo-Sung Cho ,  Soon-Moon Jung ,  Won-Seok Cho ,  Jong-Hyuk Kim ,  Jae-Hun Jeong ,  Jae-Hoon Jang

IPC: H01L31/062

CPC classification number: H01L27/11524 ,  H01L27/0688 ,  H01L27/11551

Abstract: Provided is a NAND-type nonvolatile memory device and method of forming the same. In the method, a plurality of cell layers are stacked on a semiconductor substrate. Seed contact holes for forming a semiconductor pattern included in a stacked cell are formed at regular distance. At this time, the seed contact holes are arranged such that a bit line plug or a source line pattern is disposed at a center between one pair of seed contact holes adjacent to each other.

Abstract translation: 提供了一种NAND型非易失性存储器件及其形成方法。 在该方法中，多个单元层层叠在半导体基板上。 用于形成包含在层叠电池中的半导体图案的种子接触孔以规则的距离形成。 此时，种子接触孔布置成使得位线插头或源极线图案设置在彼此相邻的一对种子接触孔之间的中心处。

公开(公告)号：US20080272434A1

公开(公告)日：2008-11-06

申请号：US11876638

申请日：2007-10-22

Applicant: Jun-Beom PARK ,  Ki-Nam KIM ,  Soon-Moon JUNG ,  Jae-Hoon JANG

Inventor： Jun-Beom PARK ,  Ki-Nam KIM ,  Soon-Moon JUNG ,  Jae-Hoon JANG

IPC: H01L27/115 ,  H01L21/8247

CPC classification number: H01L27/115 ,  H01L27/0688 ,  H01L27/11521 ,  H01L27/11551

Abstract: A non-volatile memory device and a method of manufacturing the same are disclosed. In the non-volatile memory device, first gate structures and first impurity diffusion regions are formed on a substrate. A first insulating interlayer is formed on the substrate. A semiconductor layer including second gate structures and second impurity diffusion regions is formed on the first insulating interlayer. A second insulating interlayer is formed on the semiconductor layer. A contact plug connecting the first impurity diffusion regions to the second impurity diffusion regions is formed. A common source line connected to the contact plug is formed on the second insulating interlayer. The common source line connected to the first and second impurity diffusion regions is formed over a top semiconductor layer.

Abstract translation: 公开了一种非易失性存储器件及其制造方法。 在非易失性存储器件中，在衬底上形成第一栅极结构和第一杂质扩散区。 在基板上形成第一绝缘中间层。 在第一绝缘中间层上形成包括第二栅极结构和第二杂质扩散区的半导体层。 在半导体层上形成第二绝缘中间层。 形成将第一杂质扩散区域连接到第二杂质扩散区域的接触插塞。 在第二绝缘中间层上形成连接到接触塞的共同源极线。 连接到第一和第二杂质扩散区的公共源极线形成在顶部半导体层上。

公开(公告)号：US20080067517A1

公开(公告)日：2008-03-20

申请号：US11655115

申请日：2007-01-19

Applicant: Young-Chul Jang ,  Won-Seok Cho ,  Jae-Hoon Jang ,  Soon-Moon Jung ,  Yang-Soo Son ,  Min-Sung Song

Inventor： Young-Chul Jang ,  Won-Seok Cho ,  Jae-Hoon Jang ,  Soon-Moon Jung ,  Yang-Soo Son ,  Min-Sung Song

IPC: H01L29/772 ,  H01L21/8234

CPC classification number: H01L27/0688 ,  H01L27/105 ,  H01L27/11519 ,  H01L27/11526 ,  H01L27/11529 ,  H01L27/11551

Abstract: A semiconductor device includes a semiconductor substrate including a first region having a cell region and a second region having a peripheral circuit region, first transistors on the semiconductor substrate, a first protective layer covering the first transistors, a first insulation layer on the first protective layer, a semiconductor pattern on the first insulation layer in the first region, second transistors on the semiconductor pattern, a second protective layer covering the second transistors, the second protective layer having a thickness greater than that of the first protective layer, and a second insulation layer on the second protective layer and the first insulation layer of the second region.

Abstract translation: 半导体器件包括：半导体衬底，包括具有单元区域的第一区域和具有外围电路区域的第二区域;半导体衬底上的第一晶体管;覆盖第一晶体管的第一保护层;第一保护层上的第一绝缘层; ，第一区域中的第一绝缘层上的半导体图案，半导体图案上的第二晶体管，覆盖第二晶体管的第二保护层，第二保护层的厚度大于第一保护层的厚度，第二绝缘层 在第二保护层和第二区域的第一绝缘层上。

公开(公告)号：US09747995B2

公开(公告)日：2017-08-29

申请号：US15176269

申请日：2016-06-08

Applicant: Sun-Il Shim ,  Jae-Hoon Jang ,  Donghyuk Chae ,  Youngho Lim ,  Hansoo Kim ,  Jaehun Jeong

Inventor： Sun-Il Shim ,  Jae-Hoon Jang ,  Donghyuk Chae ,  Youngho Lim ,  Hansoo Kim ,  Jaehun Jeong

IPC: G11C16/10 ,  G11C16/34 ,  G11C16/04 ,  H01L27/11582 ,  G11C16/08 ,  G11C16/12 ,  G11C16/14 ,  G11C16/26 ,  H01L27/1157

CPC classification number: G11C16/3459 ,  G11C16/0483 ,  G11C16/08 ,  G11C16/10 ,  G11C16/12 ,  G11C16/14 ,  G11C16/26 ,  G11C16/3418 ,  H01L27/1157 ,  H01L27/11582

Abstract: Nonvolatile memory devices, operating methods thereof, and memory systems including the same. A nonvolatile memory device may include a memory cell array and a word line driver. The memory cell array may include a plurality of memory cells. The word line driver may be configured to apply word line voltages to a plurality of word lines connected to the plurality of memory cells, respectively. Magnitudes of the word line voltages may be determined according to locations of the plurality of word lines.

公开(公告)号：US08923053B2

公开(公告)日：2014-12-30

申请号：US14029100

申请日：2013-09-17

Applicant: Jinman Han ,  Sunil Shim ,  Hansoo Kim ,  Jae-Hoon Jang ,  Byoungkeun Son

Inventor： Jinman Han ,  Sunil Shim ,  Hansoo Kim ,  Jae-Hoon Jang ,  Byoungkeun Son

IPC: G11C16/04 ,  G11C16/34 ,  H01L27/115 ,  G11C16/16 ,  G11C16/10 ,  H01L29/792

CPC classification number: G11C16/04 ,  G11C16/10 ,  G11C16/16 ,  G11C16/3418 ,  H01L27/11578 ,  H01L27/11582 ,  H01L29/7926

Abstract: Provided is a method of operating a nonvolatile memory device that includes a substrate and memory blocks having a plurality of memory cells stacked along a direction perpendicular to the substrate. The method includes: reading data from a selected sub block among sub blocks of a selected memory block and selectively refreshing each sub block of the selected memory block in response to the reading of the selected sub block, wherein each sub block of the selected memory block is separately erased.

Abstract translation: 提供了一种操作包括基板的非易失性存储器件的方法和具有沿着垂直于衬底的方向堆叠的多个存储单元的存储器块。 该方法包括：响应于所选择的子块的读取，从所选择的存储器块的子块中读取选定的子块的数据并选择刷新所选存储块的每个子块，其中所选存储块的每个子块 被单独擦除。

公开(公告)号：US08879321B2

公开(公告)日：2014-11-04

申请号：US12817793

申请日：2010-06-17

Applicant: Sung-min Hwang ,  Han-soo Kim ,  Won-seok Cho ,  Jae-hoon Jang

Inventor： Sung-min Hwang ,  Han-soo Kim ,  Won-seok Cho ,  Jae-hoon Jang

IPC: G11C16/04 ,  H01L27/115

CPC classification number: H01L27/11582 ,  G11C16/0483 ,  H01L21/265 ,  H01L21/28518 ,  H01L21/30604 ,  H01L21/768 ,  H01L27/11578 ,  H01L29/6656

Abstract: Provided is a vertical non-volatile memory device having a metal source line. The vertical non-volatile memory device includes cell string units that are formed on first portions of a semiconductor substrate and are vertically arranged with respect to a surface of the semiconductor substrate, impurity regions formed on second portions of the semiconductor substrate between the cell string units, conductive lines formed on the impurity regions, and spacers that are formed on the sidewalls of the cell string units and insulate the conductive lines from the cells string units.

Abstract translation: 提供了具有金属源线的垂直非易失性存储器件。 垂直非易失性存储器件包括形成在半导体衬底的第一部分上且相对于半导体衬底的表面垂直布置的单元串单元，形成在半导体衬底的第二部分之间的细胞串单元 在杂质区上形成的导电线，以及形成在电池串单元的侧壁上的间隔物，并使导电线与电池串单元绝缘。

公开(公告)号：US08772857B2

公开(公告)日：2014-07-08

申请号：US13221380

申请日：2011-08-30

Applicant: Byeong-In Choe ,  Jae-Hoon Jang ,  Sun-Il Shim ,  Han-Soo Kim ,  Jin-Man Han

Inventor： Byeong-In Choe ,  Jae-Hoon Jang ,  Sun-Il Shim ,  Han-Soo Kim ,  Jin-Man Han

IPC: H01L29/788

CPC classification number: H01L27/11582 ,  H01L29/7926

Abstract: A vertical memory device includes a channel, a ground selection line (GSL), word lines and a string selection line (SSL). The channel extends in a first direction substantially perpendicular to a top surface of a substrate, and a thickness of the channel is different according to height. The GSL, the word lines and the SSL are sequentially formed on a sidewall of the channel in the first direction and spaced apart from each other.

Abstract translation: 垂直存储器件包括通道，接地选择线（GSL），字线和字符串选择线（SSL）。 通道沿基本上垂直于基板的顶表面的第一方向延伸，并且通道的厚度根据高度而不同。 GSL，字线和SSL顺序地形成在通道的第一方向的侧壁上并且彼此间隔开。

公开(公告)号：US08324675B2

公开(公告)日：2012-12-04

申请号：US12644976

申请日：2009-12-22

Applicant: Hui-chang Moon ,  Han-soo Kim ,  Won-seok Cho ,  Jae-hoon Jang ,  Ki-hyun Kim

Inventor： Hui-chang Moon ,  Han-soo Kim ,  Won-seok Cho ,  Jae-hoon Jang ,  Ki-hyun Kim

IPC: H01L29/76

CPC classification number: H01L27/11578 ,  H01L27/11582 ,  H01L29/792 ,  H01L29/7926

Abstract: A flash memory device having a vertical channel structure. The flash memory device includes a substrate having a surface that extends in a first direction, a channel region having a pillar shape and extending from the substrate in a second direction that is perpendicular to the first direction, a gate dielectric layer formed around the channel region, a memory cell string comprising a plurality of transistors sequentially formed around the channel region in the second direction, wherein the gate dielectric layer is disposed between the plurality of transistors and the channel region, and a bit line connected to one of the plurality of transistors, and surrounding a side wall and an upper surface of one end of the channel region so as to directly contact the channel region.

Abstract translation: 一种具有垂直通道结构的闪速存储器件。 闪速存储装置包括：具有沿第一方向延伸的表面的基板，具有柱状的沟道区域，并且在与第一方向垂直的第二方向上从基板延伸;栅极介电层，形成在沟道区域周围 ，包括在所述第二方向上依次形成在所述沟道区周围的多个晶体管的存储单元串，其中所述栅介质层设置在所述多个晶体管和所述沟道区之间，并且位线连接到所述多个晶体管中的一个晶体管 并且围绕通道区域的一端的侧壁和上表面，以便直接接触通道区域。

公开(公告)号：US08295089B2

公开(公告)日：2012-10-23

申请号：US12658072

申请日：2010-02-02

Applicant: Jae-hun Jeong ,  Han-soo Kim ,  Won-seok Cho ,  Jae-hoon Jang ,  Sun-il Shim

Inventor： Jae-hun Jeong ,  Han-soo Kim ,  Won-seok Cho ,  Jae-hoon Jang ,  Sun-il Shim

IPC: G11C16/04

CPC classification number: G11C16/0483 ,  G11C16/10 ,  G11C16/26 ,  H01L23/5226 ,  H01L27/11524 ,  H01L27/11551 ,  H01L27/11556 ,  H01L27/11582 ,  H01L29/66825 ,  H01L29/7881

Abstract: A non-volatile memory device having a vertical structure includes a NAND string having a vertical structure. The NAND string includes a plurality of memory cells, and at least one pair of first selection transistors arranged to be adjacent to a first end of the plurality of memory cells. A plurality of word lines are coupled to the plurality of memory cells of the NAND string. A first selection line is commonly connected to the at least one pair of first selection transistors of the NAND string.

Abstract translation: 具有垂直结构的非易失性存储器件包括具有垂直结构的NAND串。 NAND串包括多个存储单元，并且至少一对第一选择晶体管布置成与多个存储单元的第一端相邻。 多个字线耦合到NAND串的多个存储单元。 第一选择线通常连接到NAND串的至少一对第一选择晶体管。

公开(公告)号：US08258563B2

公开(公告)日：2012-09-04

申请号：US13049495

申请日：2011-03-16

Applicant: Young-Chul Jang ,  Ki-Nam Kim ,  Soon-Moon Jung ,  Jae-Hoon Jang

Inventor： Young-Chul Jang ,  Ki-Nam Kim ,  Soon-Moon Jung ,  Jae-Hoon Jang

IPC: H01L29/76

CPC classification number: H01L27/105 ,  H01L21/8221 ,  H01L27/0688 ,  H01L27/115 ,  H01L27/11521 ,  H01L27/11524 ,  H01L27/11526 ,  H01L27/11529 ,  H01L27/11551

Abstract: A nonvolatile memory device includes a semiconductor substrate having a first well region of a first conductivity type, and at least one semiconductor layer formed on the semiconductor substrate. A first cell array is formed on the semiconductor substrate, and a second cell array formed on the semiconductor layer. The semiconductor layer includes a second well region of the first conductivity type having a doping concentration greater than a doping concentration of the first well region of the first conductivity type. As the doping concentration of the second well region is increased, a resistance difference may be reduced between the first and second well regions.

Abstract translation: 非易失性存储器件包括具有第一导电类型的第一阱区和形成在半导体衬底上的至少一个半导体层的半导体衬底。 第一单元阵列形成在半导体衬底上，第二单元阵列形成在半导体层上。 半导体层包括第一导电类型的第二阱区，其具有大于第一导电类型的第一阱区的掺杂浓度的掺杂浓度。 随着第二阱区域的掺杂浓度增加，可以在第一和第二阱区域之间减小电阻差。