公开(公告)号：US08117363B2

公开(公告)日：2012-02-14

申请号：US12750906

申请日：2010-03-31

Applicant: Jung-bae Lee

Inventor： Jung-bae Lee

IPC: G06F13/00 ,  H03K17/16 ,  H03K19/003 ,  G11C7/06 ,  G11C5/14

CPC classification number: G11C5/00 ,  G11C5/06 ,  G11C7/1048 ,  G11C11/409 ,  H05K1/0246

Abstract: A memory module and a related memory system are disclosed. The memory module comprises a semiconductor memory having a data output buffer, a data input buffer, a command/address input buffer and a first termination resistor unit connected to a data bus. The memory module further comprises a second termination resistor unit connected to an internal command/address bus. First and second termination resistor units are preferably of different resistive value and/or type.

Abstract translation: 公开了一种存储器模块和相关存储器系统。 存储器模块包括具有数据输出缓冲器，数据输入缓冲器，连接到数据总线的命令/地址输入缓冲器和第一终端电阻器单元的半导体存储器。 存储器模块还包括连接到内部命令/地址总线的第二终端电阻器单元。 第一和第二终端电阻器单元优选地具有不同的电阻值和/或类型。

公开(公告)号：US08042404B2

公开(公告)日：2011-10-25

申请号：US12128159

申请日：2008-05-28

Applicant: Young-Chan Jang ,  Jung-Bae Lee ,  Yun-Sang Lee

Inventor： Young-Chan Jang ,  Jung-Bae Lee ,  Yun-Sang Lee

IPC: G01L1/00

CPC classification number: G01R31/2849 ,  G01R31/2621 ,  G01R31/2642 ,  G11C29/12 ,  G11C29/50

Abstract: A stress detection circuit includes a function block and a detection signal generation circuit. The function block outputs a first voltage such that the first voltage is varied depending on an extent that the function block is stressed. The detection signal generation circuit generates a stress detection signal based on the first voltage and a second voltage during a test mode. The stress detection signal represents integration of the function block, and a level of the second voltage corresponds to a level of the first voltage before the function block is stressed.

Abstract translation: 应力检测电路包括功能块和检测信号生成电路。 功能块输出第一电压，使得第一电压根据功能块受应力的程度而变化。 检测信号发生电路在测试模式期间产生基于第一电压和第二电压的应力检测信号。 应力检测信号表示功能块的积分，第二电压的电平对应于在功能块受到应力之前的第一电压的电平。

公开(公告)号：US20110248740A1

公开(公告)日：2011-10-13

申请号：US13163884

申请日：2011-06-20

Applicant: Hoe ju CHUNG ,  Jung bae LEE ,  Hoon LEE

Inventor： Hoe ju CHUNG ,  Jung bae LEE ,  Hoon LEE

IPC: G01R31/26

CPC classification number: H01L22/22 ,  H01L25/0657 ,  H01L25/18 ,  H01L2224/05573 ,  H01L2224/16145 ,  H01L2225/06503 ,  H01L2225/06513 ,  H01L2924/01019 ,  H01L2924/01021 ,  H01L2924/01055

Abstract: The present invention provides an apparatus including a stacked plurality of devices and a related method. The apparatus includes a stacked plurality of devices including a master device and at least one secondary device; a plurality of segments, each segment being associated with one of the stacked plurality of devices; and a plurality of N vertical connection paths traversing the stacked plurality of devices. The apparatus further includes a plurality of M vertical signal paths configured from the plurality of N vertical connections paths, wherein M is less than N, and at least one of the plurality of M vertical signal paths is a merged vertical signal path adaptively configured by the master device using at least one segment from each one of at least two of the plurality of N vertical connection paths.

Abstract translation: 本发明提供一种包括堆叠的多个装置和相关方法的装置。 该装置包括堆叠的多个装置，包括主装置和至少一个次装置; 多个段，每个段与堆叠的多个设备中的一个相关联; 以及穿过堆叠的多个装置的多个N个垂直连接路径。 该装置还包括由多个N个垂直连接路径构成的多个M个垂直信号路径，其中M小于N，并且多个M个垂直信号路径中的至少一个是被自动配置的合并垂直信号路径 主设备使用来自多个N个垂直连接路径中的至少两个中的每一个的至少一个段。

公开(公告)号：US08010859B2

公开(公告)日：2011-08-30

申请号：US11779977

申请日：2007-07-19

Applicant: Jung-Bae Lee

Inventor： Jung-Bae Lee

IPC: H04L1/18

CPC classification number: H04L1/1671 ,  H04L1/0025 ,  H04L25/0272 ,  H04L25/0278 ,  H04L25/0288 ,  H04L25/03038 ,  H04L25/03057 ,  H04L25/03885

Abstract: A system having a transmission unit transmitting an output data signal formed from output data and related error detection code and a corresponding receiving unit. The output data signal is pre-emphasized by a pre-emphasis driver in the transmission unit. The receiving unit includes an equalizer equalizing the received output data signal and an error detector analyzing the error detection code to determine whether a bit error is present in the received data. Upon successive data transmission failures either an equalization coefficient in the equalizer or a pre-emphasis coefficient in the pre-emphasis driver are changed.

Abstract translation: 一种具有发送单元的系统，该发送单元发送由输出数据和相关错误检测码形成的输出数据信号和相应的接收单元。 输出数据信号由传输单元中的预加重驱动器预先强调。 接收单元包括均衡接收的输出数据信号的均衡器和分析错误检测码的误差检测器，以确定接收数据中是否存在位错误。 在连续数据传输故障时，均衡器中的均衡系数或预加重驱动器中的预加重系数被改变。

公开(公告)号：US20110093235A1

公开(公告)日：2011-04-21

申请号：US12900547

申请日：2010-10-08

Applicant: CHI-SUNG OH ,  Dong-Hyuk Lee ,  Ho-Cheol Lee ,  Jang-Woo Ryu ,  Jung-Bae Lee

Inventor： CHI-SUNG OH ,  Dong-Hyuk Lee ,  Ho-Cheol Lee ,  Jang-Woo Ryu ,  Jung-Bae Lee

IPC: G01R31/14 ,  H03L7/00

CPC classification number: G01R31/2884 ,  G01R31/31726

Abstract: A semiconductor device is provided. The semiconductor device applies data applied through a bump pad on which a bump is mounted through a test pad to a test apparatus such that the reliability of the test can be improved. The amount of test pads is significantly reduced by allowing data output through bump pads to be selectively applied to a test pad. Data and signals applied from test pads are synchronized with each other and applied to bump pads during a test operation such that the reliability of the test can be improved without the need of an additional test chip.

Abstract translation: 提供半导体器件。 半导体器件将通过测试焊盘安装有凸块的凸块焊盘施加的数据施加到测试装置，使得可以提高测试的可靠性。 通过允许通过凸块焊盘的数据输出被选择性地施加到测试焊盘，测试焊盘的量显着减少。 从测试焊盘施加的数据和信号彼此同步，并在测试操作期间应用于凸块焊盘，从而可以提高测试的可靠性，而无需额外的测试芯片。

公开(公告)号：US20110069572A1

公开(公告)日：2011-03-24

申请号：US12832208

申请日：2010-07-08

Applicant: Dong-Hyuk Lee ,  Jung-Bae Lee ,  Ki-Won Park

Inventor： Dong-Hyuk Lee ,  Jung-Bae Lee ,  Ki-Won Park

IPC: G11C7/00

CPC classification number: G11C11/406 ,  G11C11/40618 ,  G11C11/40622 ,  G11C17/16 ,  G11C2211/4061

Abstract: A memory device identifies memory blocks that contain substandard memory cells. The memory device then determines row address codes to apply to the memory blocks during refresh operations. The row address codes determine which memory blocks of the memory block are refreshed together. The row address codes are designed to ensure that memory blocks having substandard memory cells, which must be refreshed more frequently than other cells, are refreshed together, while memory blocks without substandard memory cells are refreshed together.

Abstract translation: 存储器设备识别包含不合标准存储器单元的存储器块。 然后，存储器件在刷新操作期间确定应用于存储器块的行地址代码。 行地址代码确定存储器块的哪些存储器块被一起刷新。 行地址码被设计为确保具有不同于其它单元的频率更新的不合格存储器单元的存储器块被一起刷新，而没有不合格存储器单元的存储器块被刷新在一起。

公开(公告)号：US07894241B2

公开(公告)日：2011-02-22

申请号：US12326940

申请日：2008-12-03

Applicant: Yun-Sang Lee ,  Woo-Jung Sun ,  Jung-Bae Lee

Inventor： Yun-Sang Lee ,  Woo-Jung Sun ,  Jung-Bae Lee

IPC: G11C7/00

CPC classification number: G11C11/4091 ,  G11C7/065 ,  G11C7/12 ,  G11C11/4094

Abstract: A memory cell array with open bit line structure includes a first sub memory cell array, a second sub memory cell array, a sense-amplifier/precharge circuit, first capacitors and second capacitors. The first sub memory cell array is activated in response to a first word line enable signal, and the second sub memory cell array is activated in response to a second word line enable signal. The sense-amplifier/precharge circuit is connected to the first sub memory cell array through first bit lines and to the second sub memory cell array through second bit lines, and the sense-amplifier/precharge circuit precharges the first bit lines and the second bit lines and amplifies data provided from the first sub memory cell array and the second sub memory cell array.

Abstract translation: 具有开放位线结构的存储单元阵列包括第一子存储单元阵列，第二子存储单元阵列，读出放大器/预充电电路，第一电容器和第二电容器。 第一子存储单元阵列响应于第一字线使能信号被激活，并且第二子存储单元阵列响应于第二字线使能信号被激活。 感测放大器/预充电电路通过第一位线连接到第一子存储单元阵列，并通过第二位线连接到第二子存储单元阵列，并且读出放大器/预充电电路对第一位线和第二位进行预充电 并且放大从第一子存储单元阵列和第二子存储单元阵列提供的数据。

公开(公告)号：US20100226185A1

公开(公告)日：2010-09-09

申请号：US12781936

申请日：2010-05-18

Applicant: Jung-bae Lee

Inventor： Jung-bae Lee

IPC: G11C7/10 ,  G11C5/14 ,  G11C5/02

CPC classification number: G11C7/1078 ,  G11C5/04 ,  G11C7/1084

Abstract: A semiconductor memory module includes a memory module board having at least one semiconductor memory device, an advanced memory buffer (AMB) for receiving the data and the command/address signal from a host and providing the data and the command/address signal to the at least one semiconductor memory device, and a second termination resistor unit located on the memory module board and electrically connected to the AMB. The at least one semiconductor memory device includes a data input buffer for receiving data via a first input terminal and receiving a first reference voltage via a second input terminal, a command/address input buffer for receiving a command/address signal via a first input terminal and receiving a second reference voltage via a second input terminal, and a first termination resistor unit connected to the first input terminal of the data input buffer.

Abstract translation: 半导体存储器模块包括具有至少一个半导体存储器件的存储器模块板，用于从主机接收数据和命令/地址信号的高级存储器缓冲器（AMB），并将数据和命令/地址信号提供给at 至少一个半导体存储器件，以及位于存储器模块板上并电连接到AMB的第二终端电阻器单元。 所述至少一个半导体存储器件包括用于经由第一输入端子接收数据并经由第二输入端子接收第一参考电压的数据输入缓冲器，用于经由第一输入端子接收命令/地址信号的命令/地址输入缓冲器 以及经由第二输入端子接收第二参考电压，以及连接到数据输入缓冲器的第一输入端的第一终端电阻器单元。

公开(公告)号：US07692983B2

公开(公告)日：2010-04-06

申请号：US11745965

申请日：2007-05-08

Applicant: Jung-Bae Lee ,  Hoe-Ju Chung

Inventor： Jung-Bae Lee ,  Hoe-Ju Chung

IPC: G11C5/02 ,  H03H7/38

CPC classification number: G06F13/1673 ,  G06F13/1684

Abstract: The invention provides an improved memory system that addresses signal degradation due to transmission line effects. The improved memory system includes a first buffer, at least one first memory device coupled to the first buffer, and a plurality of signal traces. The first buffer and memory device are mounted on a motherboard. Likewise, the plurality of signal traces is routed on the motherboard. Doing so eliminates stub loads that cause signal reflection that, in turn, result in signal degradation.

Abstract translation: 本发明提供了一种改进的存储器系统，其解决了由于传输线效应引起的信号劣化 改进的存储器系统包括第一缓冲器，耦合到第一缓冲器的至少一个第一存储器件和多个信号迹线。 第一个缓冲器和存储器件安装在主板上。 同样地，多个信号迹线在主板上路由。 这样做可以消除引起信号反射的短线负载，从而导致信号衰减。

公开(公告)号：US07679985B2

公开(公告)日：2010-03-16

申请号：US11863141

申请日：2007-09-27

Applicant: Chul-Woo Park ,  Sung-Hoon Kim ,  Hyuk-Joon Kwon ,  Jung-Bae Lee ,  Youn-Sik Park

Inventor： Chul-Woo Park ,  Sung-Hoon Kim ,  Hyuk-Joon Kwon ,  Jung-Bae Lee ,  Youn-Sik Park

IPC: G11C8/00

CPC classification number: H01L27/0207 ,  G11C5/025 ,  G11C5/063 ,  G11C7/18 ,  H01L23/5226 ,  H01L27/0203 ,  H01L27/105 ,  H01L27/1052 ,  H01L27/10897 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A semiconductor memory device and an arrangement method thereof are disclosed. The semiconductor memory device comprises column selecting signal lines and global data IO signal lines arranged on the same layer in the same direction above a memory cell array; word lines and first local data IO signal lines arranged on a different layer from the column selecting signal lines above the memory cell array, in a perpendicular direction to the column selecting signal lines; and second local data IO signal lines arranged on a different layer from the column selecting signal lines and the word lines above the memory cell array, in the same direction as the first local data IO signal lines.

Abstract translation: 公开了一种半导体存储器件及其布置方法。 半导体存储器件包括在存储单元阵列上方沿相同方向布置在同一层上的列选择信号线和全局数据IO信号线; 在与列选择信号线垂直的方向上与位于存储单元阵列上方的列选择信号线布置在不同层上的字线和第一本地数据IO信号线; 以及在与第一本地数据IO信号线相同的方向上与列选择信号线和存储单元阵列上方的字线​​布置在不同层上的第二本地数据IO信号线。