公开(公告)号：US20090116302A1

公开(公告)日：2009-05-07

申请号：US12215738

申请日：2008-06-30

Applicant: Kyung-Hoon Kim ,  Sang-Yeon Byeon ,  Chang-Kyu Choi

Inventor： Kyung-Hoon Kim ,  Sang-Yeon Byeon ,  Chang-Kyu Choi

IPC: G11C7/00 ,  G11C8/18

CPC classification number: G11C7/22 ,  G11C7/1066 ,  G11C7/222 ,  G11C11/4076

Abstract: A semiconductor memory device can a desired internal clock in consideration of a delay time of an actual clock/data path. The semiconductor memory device includes a multiclock signal generating unit configured to receive a reference clock signal and generate a plurality of clock signals having a constant phase difference from each other, a delay modeling unit configured to generate a plurality of delay clock signals by reflecting a delay time of an actual clock/data path to the plurality of clock signals, a selection signal generating unit configured to generate selection signals by comparing phases between the reference clock signal and the plurality of delay clock signals, and a phase multiplexing unit configured to output any one of the plurality of clock signals as a final clock signal in response to the selection signals.

Abstract translation: 考虑到实际时钟/数据路径的延迟时间，半导体存储器件可以具有期望的内部时钟。 半导体存储器件包括多锁信号产生单元，被配置为接收参考时钟信号并产生彼此具有恒定相位差的多个时钟信号;延迟建模单元，被配置为通过反映延迟来产生多个延迟时钟信号 选择信号生成单元，被配置为通过比较参考时钟信号和多个延迟时钟信号之间的相位来产生选择信号;以及相位多路复用单元，被配置为输出任意的时钟/数据路径， 所述多个时钟信号中的一个作为响应于所述选择信号的最终时钟信号。

公开(公告)号：US07436230B2

公开(公告)日：2008-10-14

申请号：US10746226

申请日：2003-12-23

Applicant: Kyung-Hoon Kim

Inventor： Kyung-Hoon Kim

IPC: H03L7/06

CPC classification number: G11C7/222 ,  G11C7/22 ,  H03L7/0814 ,  H03L7/085

Abstract: A delay locked loop can remove a jitter component that inevitably occurs due to feedback latency in the conventional DLL. That is, the present invention has benefit of removing the jitter component by controlling the delay lines based on the predicted data. The delay locked loop includes a pattern detecting unit for generating and storing a noise pattern by detecting inputted noise data, a pre-delay control unit for determining a delay amount depending on the output of the pattern detecting unit, and a pre-delay line for delaying an internal clock depending on the delay amount that is determined by the pre-delay control means.

Abstract translation: 延迟锁定环可以消除由于常规DLL中的反馈等待时间而不可避免地发生的抖动分量。 也就是说，本发明通过基于预测数据控制延迟线来消除抖动分量的益处。 延迟锁定环包括：图案检测单元，用于通过检测输入的噪声数据产生和存储噪声模式;预延迟控制单元，用于根据模式检测单元的输出确定延迟量;以及预延迟线， 根据由预延迟控制装置确定的延迟量来延迟内部时钟。

公开(公告)号：US20080238502A1

公开(公告)日：2008-10-02

申请号：US12003676

申请日：2007-12-31

Applicant: Taek-Sang Song ,  Kyung-Hoon Kim ,  Dae-Han Kwon

Inventor： Taek-Sang Song ,  Kyung-Hoon Kim ,  Dae-Han Kwon

IPC: H03L7/08 ,  H03H11/26

CPC classification number: H03L7/0995 ,  H03K3/0322 ,  H03K5/133 ,  H03K2005/00208 ,  H03K2005/00234 ,  H03L2207/06

Abstract: A phase locked loop that generates an internal clock by controlling a delay time of a delay cell according to conditions of PVT, thereby improving a jitter characteristic of the internal clock. The delay cell includes a first current controller for controlling first and second currents in response to a control voltage, and a second current controller for controlling the first and second currents in response to frequency range selection signals. The phase locked loop includes a phase comparator for comparing a reference clock with a feedback clock, a control voltage generator for generating a control voltage corresponding to an output of the phase comparator, and a voltage controlled oscillator for generating an internal clock having a frequency in response to the control voltage and one or more frequency range control signals, wherein the feedback clock is generated using the internal clock.

Abstract translation: 通过根据PVT的条件控制延迟单元的延迟时间来产生内部时钟的锁相环，从而提高内部时钟的抖动特性。 延迟单元包括响应于控制电压控制第一和第二电流的第一电流控制器，以及响应频率范围选择信号控制第一和第二电流的第二电流控制器。 锁相环包括用于将参考时钟与反馈时钟进行比较的相位比较器，用于产生对应于相位比较器的输出的控制电压的控制电压发生器和用于产生具有频率的内部时钟的压控振荡器 响应于控制电压和一个或多个频率范围控制信号，其中使用内部时钟产生反馈时钟。

公开(公告)号：US20080223067A1

公开(公告)日：2008-09-18

申请号：US12073813

申请日：2008-03-10

Applicant: Seong Je Wu ,  Dong Kwan Kim ,  Kyung Hoon Kim

Inventor： Seong Je Wu ,  Dong Kwan Kim ,  Kyung Hoon Kim

IPC: F25B27/00 ,  H01M8/02

CPC classification number: H01M8/04776 ,  B60H1/00392 ,  B60H1/00428 ,  H01M8/04604 ,  H01M8/04619 ,  H01M8/0494 ,  H01M8/04992 ,  H01M16/006 ,  H01M2250/20 ,  Y02P70/56 ,  Y02T10/88 ,  Y02T90/32

Abstract: The air conditioner has a variable load to undergo a rapid change in instantaneous power consumption. The fuel cell system supplies electricity generated by reacting fuel with oxygen to the air conditioner. The fuel cell system stores the generated electricity if the instantaneous power consumption of the air conditioner is lowered and supplies the stored electricity together with the generated electricity to the air conditioner if the instantaneous power consumption is increased.

Abstract translation: 空调具有可变负载以瞬时功耗的快速变化。 燃料电池系统将燃料与氧气反应产生的电力供给空调。 如果空调器的瞬时功率消耗降低，则燃料电池系统存储发电，并且如果瞬时功耗增加，则将发电的电力一起供应到空调。

公开(公告)号：US20080205861A1

公开(公告)日：2008-08-28

申请号：US11877696

申请日：2007-10-24

Applicant: Kyung-hoon KIM

Inventor： Kyung-hoon KIM

IPC: H04N5/781 ,  G06F3/00

CPC classification number: H04N5/772 ,  G06F3/0482 ,  H04N5/765 ,  H04N5/85 ,  H04N5/907 ,  H04N9/7921 ,  H04N9/8042 ,  H04N9/8047

Abstract: Provided are an apparatus and method of recording an optical disc. The apparatus includes a reader which reads image files defined by a user from a storage medium, in which the image files are stored, a screen information generator which generates title menu screen information using the read image files, and a record controller which records the generated title menu screen information on the optical disc.

Abstract translation: 提供一种记录光盘的装置和方法。 该装置包括读取器，其从存储有图像文件的存储介质读取由用户定义的图像文件，使用所读取的图像文件生成标题菜单屏幕信息的屏幕信息生成器，以及记录控制器， 标题菜单屏幕信息在光盘上。

公开(公告)号：US20080204597A1

公开(公告)日：2008-08-28

申请号：US11855438

申请日：2007-09-14

Applicant: Kyung-hoon KIM

Inventor： Kyung-hoon KIM

IPC: H04N5/445

CPC classification number: H04N5/45 ,  H04N21/4316 ,  H04N21/4858 ,  H04N21/4882

Abstract: Provided are a method and apparatus for reproducing moving picture data which includes sub-screen picture data. The method includes outputting messages indicating that the moving picture data includes the sub-screen picture data, receiving a selection on whether to display the sub-screen picture data, and selectively displaying the sub-screen picture data according to the selection. Accordingly, the sub-screen picture data can be selectively displayed.

Abstract translation: 提供了一种用于再现包括子屏幕图像数据的运动图像数据的方法和装置。 该方法包括输出指示运动图像数据包括子屏幕图像数据的消息，接收关于是否显示子屏幕图像数据的选择，以及根据选择选择性地显示子屏幕图像数据。 因此，可以选择性地显示子屏幕图像数据。

公开(公告)号：US20080198119A1

公开(公告)日：2008-08-21

申请号：US11851762

申请日：2007-09-07

Applicant: Pil-Mo Choi ,  Kook-Chul Moon ,  Ho-Suk Maeng ,  Kwang-Sub Shin ,  Chul-Ho Kim ,  Sang-Hoon Lee ,  Kyung-Hoon Kim ,  Keun-Woo Park

Inventor： Pil-Mo Choi ,  Kook-Chul Moon ,  Ho-Suk Maeng ,  Kwang-Sub Shin ,  Chul-Ho Kim ,  Sang-Hoon Lee ,  Kyung-Hoon Kim ,  Keun-Woo Park

IPC: G09G3/36

CPC classification number: G09G3/3648

Abstract: A liquid crystal display includes a display panel having a data-storing unit including transistors integrated into the display panel. The data-storing transistors of the data-storing unit may be formed in the same film (layer) as the TFT pixel transistors on the display panel. Each of the plurality of transistors of the data-storing unit includes an input electrode connected to one of a first voltage or a second voltage depending upon a bit of stored data, and an output electrode commonly connected to a data output terminal of the data-storing unit. The data-storing unit further includes and a Serial-In, Parallel-Out shift register supplied with a reset and first and second clock signals and connected to the input electrodes of the transistors, respectively.

Abstract translation: 液晶显示器包括具有包括集成在显示面板中的晶体管的数据存储单元的显示面板。 数据存储单元的数据存储晶体管可以形成为与显示面板上的TFT像素晶体管相同的膜（层）。 数据存储单元的多个晶体管中的每一个包括根据存储的数据的位连接到第一电压或第二电压中的一个的输入电极，以及共同连接到数据存储单元的数据输出端的输出电极， 存储单元。 数据存储单元还包括分​​别提供有复位和第一和第二时钟信号并连接到晶体管的输入电极的串并并行输出移位寄存器。

公开(公告)号：US20080180127A1

公开(公告)日：2008-07-31

申请号：US12076890

申请日：2008-03-25

Applicant: Kyung-Hoon KIM

Inventor： Kyung-Hoon KIM

IPC: G01R31/02

CPC classification number: G01R31/31708 ,  G01R31/3187 ,  G11C29/02 ,  G11C29/023 ,  G11C29/028 ,  G11C29/12015 ,  G11C29/40 ,  G11C29/50 ,  G11C29/50012

Abstract: There is provided an on-chip test circuit that is capable of measuring validity of an output signal within a chip without any external measuring device. The on-chip self test circuit implemented on the same chip as a test semiconductor device includes: a test load block for receiving a test target signal; and a self test block for receiving a test target signal passing through the test load block and a test target signal inputted to an output driver together, and determining whether a change of the test target signal is within an allowable range. Accordingly, the validity of the signal outputted from the device can be measured without any expensive external measuring device. Also, when the test must be done before the packaging stage, the test can be simply performed, thereby reducing the test cost greatly.

公开(公告)号：US20080088338A1

公开(公告)日：2008-04-17

申请号：US11987937

申请日：2007-12-06

Applicant: Kyung-Hoon Kim

Inventor： Kyung-Hoon Kim

IPC: H03K19/003

CPC classification number: H04L25/0278 ,  G01R31/31715 ,  G11C29/02 ,  G11C29/022 ,  G11C29/50008 ,  G11C2207/2254

Abstract: A semiconductor memory device includes a reference signal generating unit for generating a reference signal; a comparing unit for comparing the reference signal with a test signal applied to a test pad to output an adjusted value after adjusting the adjusted value until the test signal is equal to the reference signal; an impedance measuring unit for measuring an impedance of the test pad based on the adjusted value to output the test signal; an impedance adjusting unit for adjusting an impedance of a data I/O pad to have an impedance value corresponding to the adjusted value outputted when the test signal is equal to the reference signal; an impedance control unit for controlling the comparing unit so that the adjusted value is outputted when the test signal is equal to the reference signal; and a reference signal control unit for adjusting a voltage level of the reference signal.

Abstract translation: 半导体存储器件包括用于产生参考信号的参考信号产生单元; 比较单元，用于将参考信号与施加到测试垫的测试信号进行比较，以在调整调整值直到测试信号等于参考信号之后输出调整值; 阻抗测量单元，用于基于所述调整值来测量所述测试垫的阻抗以输出所述测试信号; 阻抗调整单元，用于调整数据I / O焊盘的阻抗，使阻抗值对应于当测试信号等于参考信号时输出的调整值; 阻抗控制单元，用于控制比较单元，使得当测试信号等于参考信号时，输出调整值; 以及用于调整参考信号的电压电平的参考信号控制单元。

公开(公告)号：US20080002493A1

公开(公告)日：2008-01-03

申请号：US11819812

申请日：2007-06-29

Applicant: Kyung-Hoon Kim ,  Yong-Ki Kim

Inventor： Kyung-Hoon Kim ,  Yong-Ki Kim

IPC: G11C29/00 ,  G11C7/00

CPC classification number: G11C29/48 ,  G11C5/04 ,  G11C29/1201 ,  G11C2029/5602

Abstract: A dual in-line memory module (DIMM) for use in test includes a memory array with a plurality of memories, a test signal input/output unit, and a normal data input/output unit. The test signal input/output unit is provided in the respective memories to perform an input/output operation of a test signal with an external test mode controller for a test mode operation. The normal data input/output unit is provided in the respective memories to perform an input/output operation of a normal data with an external memory controller for a normal mode operation.

Abstract translation: 用于测试的双列直插存储器模块（DIMM）包括具有多个存储器的存储器阵列，测试信号输入/输出单元和正常数据输入/输出单元。 测试信号输入/输出单元设置在各个存储器中，以便通过用于测试模式操作的外部测试模式控制器执行测试信号的输入/输出操作。 正常数据输入/输出单元设置在相应的存储器中，以用于正常模式操作的外部存储器控制器执行正常数据的输入/输出操作。