公开(公告)号：US20170331740A1

公开(公告)日：2017-11-16

申请号：US15152077

申请日：2016-05-11

Applicant: MELLANOX TECHNOLOGIES TLV LTD.

Inventor： Gil Levy ,  Alex Shpiner

IPC: H04L12/801 ,  H04L12/947 ,  H04L12/707

CPC classification number: H04L47/12 ,  H04L45/22 ,  H04L49/25

Abstract: Communication apparatus includes multiple interfaces configured to be connected to respective links in a packet data network. Switching circuitry in the apparatus is coupled between the interfaces and is configured to receive, via a first interface among the multiple interfaces, an adaptive routing notification (ARN) requesting that a specified flow of packets from a given source to a given destination in the network be rerouted. The switching circuitry is configured, upon verifying that the first interface serves as an egress interface for the packets in the specified flow, to reroute the specified flow through a different, second interface among the multiple interfaces when there is an alternative route available in the network from the second interface to the given destination, and after finding that there is no alternative route available from any of the interfaces to the given destination, to forward the ARN to a plurality of the interfaces.

公开(公告)号：US20170289066A1

公开(公告)日：2017-10-05

申请号：US15086990

申请日：2016-03-31

Applicant: Mellanox Technologies TLV Ltd.

Inventor： Zachy Haramaty ,  Ran Ravid ,  Oded Wertheim

IPC: H04L12/939 ,  H04L12/835 ,  H04L12/807 ,  H04L12/825

CPC classification number: H04L49/552 ,  H04L47/263 ,  H04L47/27 ,  H04L47/30

Abstract: Apparatuses and methods are described that provide for credit based flow control in a network in which a public buffer is supported at a receiver node, where a transmitter node can control the use of the public buffer. In particular, the transmitter node determines a buffer credit value (TCRi) for each virtual lane of the transmitter node. The buffer credit value (TCRi) is negative (e.g., less than 0) in an instance in which a respective virtual lane private buffer is fully used and thus reflects a loan of credits from the public buffer. In addition, the transmitter node knows the needed buffer size per virtual lane for transmitting a packet in advance based on the round trip time (RTT) and maximum transmission unit (MTU) for the packet and is precluded from consuming more space on the public buffer than required to meet RTT.

公开(公告)号：US20170270119A1

公开(公告)日：2017-09-21

申请号：US15075936

申请日：2016-03-21

Applicant: MELLANOX TECHNOLOGIES TLV LTD.

Inventor： Aviv Kfir ,  Benny Koren ,  Gil Levy ,  Barak Gafni

IPC: G06F17/30 ,  H04L9/32

CPC classification number: G06F16/2255 ,  H04L9/0643 ,  H04L9/0894

Abstract: Systems and methods are described that provide for distributively storing and accessing data across multiple hash tables, such that utilization of the hash tables is optimized. In particular, a key associated with a value is split into two or more sub-keys and the sub-keys are inserted into respective hash tables with associated values. For each sub-key except the final sub-key derived from a particular key, the value paired with the sub-key is an identifier that points to the location of the next sub-key and its associated value, which may be stored in the other hash tables. The final sub-key derived from the original key is paired with the value associated with the key, such as an action to be performed. Thus, rather than using a single key (which may be very large) to access or store a particular value, multiple (smaller) sub-keys are used to ultimately access the same value via multiple, smaller hash tables.

公开(公告)号：US09699095B2

公开(公告)日：2017-07-04

申请号：US14718114

申请日：2015-05-21

Applicant: Mellanox Technologies TLV Ltd.

Inventor： George Elias ,  Ido Bukspan ,  Noam Katz Abramovich ,  Barak Gafni

IPC: H04L12/857 ,  H04L12/851 ,  H04L12/813 ,  H04L12/823 ,  H04L29/08 ,  H04L12/927

CPC classification number: H04L47/2441 ,  H04L47/20 ,  H04L47/32 ,  H04L47/805 ,  H04L67/104

Abstract: Communication apparatus includes multiple ports for connection to a packet data network. A memory contains, for each port, a respective first, fixed headroom allocation to hold packets received from the network through the port and to contain a shared headroom buffer, which is available to be shared among a plurality of the ports. Flow-control logic allocates to each of the ports, within the shared headroom buffer, a respective second, variable headroom allocation, which varies responsively to fill levels of the respective first headroom allocation and of the shared headroom buffer, thereby defining, for each of the ports, a respective total headroom allocation comprising the respective first and second headroom allocations. The logic is configured to apply flow-control operations in response to the packets received from the network through each port responsively to a total fill level of the respective total headroom allocation of the port.

公开(公告)号：US20170163567A1

公开(公告)日：2017-06-08

申请号：US14961923

申请日：2015-12-08

Applicant: Mellanox Technologies TLV Ltd.

Inventor： Amir Roitshtein ,  Niv Aibester ,  Barak Gafni ,  George Elias

IPC: H04L12/931 ,  H04L12/861

CPC classification number: H04L49/201 ,  H04L45/745 ,  H04L49/205 ,  H04L49/9005

Abstract: Communication apparatus includes multiple interfaces connected to a packet data network. A memory is coupled to the interfaces and configured as a buffer to contain packets received through ingress interfaces while awaiting transmission to the network via respective egress interfaces. Packet processing logic is configured, upon receipt of a multicast packet through an ingress interface, to identify a number of the egress interfaces through which respective copies of the multicast packet are to be transmitted, to allocate a space in the buffer for storage of a single copy of the multicast packet, to replicate and transmit multiple copies of the stored copy of the multicast packet through the egress interfaces, to maintain a count of the replicated copies that have been transmitted, and when the count reaches the identified number, to release the allocated space in the buffer.

公开(公告)号：US20170094036A1

公开(公告)日：2017-03-30

申请号：US14868405

申请日：2015-09-29

Applicant: Mellanox Technologies TLV Ltd.

Inventor： Ariel Almog ,  Aviv Kfir ,  David Mozes ,  Barak Gafni

IPC: H04L29/06 ,  H04L12/743

CPC classification number: H04L69/22 ,  H04L45/7457

Abstract: A method for classification includes storing in a TCAM classification rules comprising respective tags, each including an update bit. Data items are classified by extracting a respective key from each data item, appending an update-select bit to construct an extended key, and matching the extended key to one of the tags in the TCAM. In response to an instruction to atomically replace a group of existing rules in the TCAM with new rules, the update bit is unmasked and set to the first bit value in the group of the existing rules. The new rules are stored in the TCAM, with their update bit set to a second bit value. After storing the new rules in the TCAM, the update-select bit in the extended key of the received data items is set to the second bit value.

公开(公告)号：US20170068669A1

公开(公告)日：2017-03-09

申请号：US14846777

申请日：2015-09-06

Applicant: Mellanox Technologies TLV Ltd.

Inventor： Gil Levy ,  Pedro Reviriego ,  Salvatore Pontarelli

IPC: G06F17/30

CPC classification number: G06F17/3033 ,  H04L45/7453

Abstract: Decision apparatus includes a first memory bank, containing a first table of hash composition factors, and a second memory bank, containing second and third tables of associative entries. A logic pipeline receives a sequence of data items and extracts a search key from each data item. A pre-hash circuit computes a first index by applying a first hash function to the search key. A first lookup circuit reads a hash composition factor from a location in the first memory bank indicated by the first index, and a hash circuit compute second and third indices as different combinations, determined by the hash composition factor, of second and third hash functions applied by the hash circuit to the search key. A second lookup circuit reads the entries in the second and third tables that are indicated respectively by the second and third indices.

Abstract translation: 决策装置包括第一存储体，其包含散列组合因子的第一表和包含第二和第三表的关联项的第二存储体。 逻辑流水线接收数据项序列，并从每个数据项提取搜索关键字。 预散列电路通过对搜索关键字应用第一散列函数来计算第一索引。 第一查找电路从由第一索引指示的第一存储体中的位置读取散列构成因子，并且散列电路计算第二和第三索引作为由哈希构成因子确定的应用的第二和第三散列函数应用的不同组合 通过哈希电路到搜索键。 第二查找电路读取由第二和第三索引分别指示的第二和第三表中的条目。

公开(公告)号：US11966319B2

公开(公告)日：2024-04-23

申请号：US17182266

申请日：2021-02-23

Applicant: MELLANOX TECHNOLOGIES TLV LTD.

Inventor： Vadim Gechman ,  Tamar Viclizki ,  Gaby Vanesa Diengott ,  David Slama ,  Samir Deeb ,  Shie Mannor ,  Gal Chechik

IPC: G06F11/00 ,  G06F11/30 ,  G06F11/34

CPC classification number: G06F11/3466 ,  G06F11/3006 ,  G06F11/3409

Abstract: A method for data-center management includes, in a data center including multiple components, monitoring a plurality of performance measures of the components. A set of composite metrics is automatically defined, each composite metric including a respective weighted combination of two or more performance measures from among the performance measures. Baseline values are established for the composite metrics. An anomalous deviation is detected of one or more of the composite metrics from the respective baseline values.

公开(公告)号：US11876642B2

公开(公告)日：2024-01-16

申请号：US17495824

申请日：2021-10-07

Applicant: MELLANOX TECHNOLOGIES TLV LTD.

Inventor： Richard Graham ,  Lion Levi ,  Gil Bloch ,  Daniel Marcovitch ,  Noam Bloch ,  Yong Qin ,  Yaniv Blumenfeld ,  Eitan Zahavi

IPC: H04L12/40 ,  G06F12/02 ,  H04B7/0456 ,  H04L12/44 ,  H04W24/10 ,  H04W88/06

CPC classification number: H04L12/40182 ,  G06F12/0246 ,  H04B7/0456 ,  H04L12/44 ,  H04W24/10 ,  H04W88/06

Abstract: A method in which a plurality of process are configured to hold a block of data destined for other processes, with data repacking circuitry including receiving circuitry configured to receive at least one block of data from a source process of the plurality of processes, the repacking circuitry configured to repack received data in accordance with at least one destination process of the plurality of processes, and sending circuitry configured to send the repacked data to the at least one destination process of the plurality of processes, receiving a set of data for all-to-all data exchange, the set of data being configured as a matrix, the matrix being distributed among the plurality of processes, and transposing the data by each of the plurality of processes sending matrix data from the process to the repacking circuitry, and the repacking circuitry receiving, repacking, and sending the resulting matrix data to destination processes.

公开(公告)号：US11711283B2

公开(公告)日：2023-07-25

申请号：US17198298

申请日：2021-03-11

Applicant: MELLANOX TECHNOLOGIES TLV LTD.

Inventor： Alan Lo ,  Matty Kadosh ,  Marian Pritsak ,  Yonatan Piasetsky

IPC: H04L43/0864 ,  H04W24/08 ,  H04L43/106

CPC classification number: H04L43/0864 ,  H04L43/106 ,  H04W24/08

Abstract: In one embodiment, a system includes a first data communication device including packet processing circuitry to provide a probe packet including an egress timestamp TS1 indicating a time at which the probe packet egresses the first data communication device, and a network interface to send the probe packet via at least one network connection to a second data communication device, and receive from the second data communication device a response packet including the egress timestamp TS1, wherein the packet processing circuitry is configured to associate with the response packet an ingress timestamp TS2 indicating a time at which the response packet ingresses the first data communication device, and a network metric processor to compute a data latency in the at least one network connection responsively to TS1, TS2, and an indication of an internal latency of the probe packet in the second data communication device.