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公开(公告)号：US20240047603A1
公开(公告)日：2024-02-08
申请号：US17881927
申请日：2022-08-05
Applicant: Mellanox Technologies, Ltd.
Inventor： Oren STEINBERG , Anders Gösta LARSSON , Attila FÜLÖP , Elad MENTOVICH , Isabelle CESTIER , Moshe B. ORON
IPC: H01L31/18 , H01L31/109 , H01L31/0304
CPC classification number: H01L31/1848 , H01L31/109 , H01L31/03048
Abstract: Processes for continuous compositional grading for realization of low charge carrier barriers in electro-optical heterostructure semiconductor devices are provided. An example process includes forming, onto one or more semiconductor layers of an electro-optical semiconductor device, a first semiconductor layer associated with a first bandgap value and forming, onto the first semiconductor layer, a grading layer associated with a continuous compositional grading. The example method further includes forming, onto the grading layer, a second semiconductor layer associated with a second bandgap value. The second bandgap value is different than the first bandgap value.
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公开(公告)号：US20240045418A1
公开(公告)日：2024-02-08
申请号：US17887642
申请日：2022-08-15
Applicant: MELLANOX TECHNOLOGIES, LTD.
Inventor： Siddha Ganju , Elad Mentovich , Dimitrios Kalavrouziotis , Paraskevas Bakopoulos , Dimitrios Syrivelis , Nikolaos Argyris , Yoram Zer , Maoz Menachem Nagler , Holger Prüsse Orup , Finn Leif Kraemer
CPC classification number: G05B23/0283 , G01R31/088 , G05B23/0254 , G05B23/0216 , G05B2223/02
Abstract: Apparatuses, systems, and techniques to monitor health data from components and predict needs for maintenance. In at least one embodiment, monitoring health data of cables having one or more known characteristics ands analyzing the health data to determine the health metrics of the one or more cable to generate profiles of the cables used to predict future health metrics of the cables and related cables sharing known characteristics.
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公开(公告)号：US11894847B1
公开(公告)日：2024-02-06
申请号：US17884878
申请日：2022-08-10
Applicant: Mellanox Technologies, Ltd.
Inventor： Igal Kushnir , Naor Peretz , Roi Levi
IPC: H03K3/017 , H04L25/03 , H03K19/0185 , H03K19/17784
CPC classification number: H03K3/017 , H03K19/018521 , H03K19/17784 , H04L25/03878
Abstract: Technologies for jitter extraction are described. A receiver device includes an analog-to-digital converter (ADC) and a signal processing circuit. The signal processing circuit includes an equalizer block to output current data based on samples from the ADC. A clock-recovery (CR) block includes a timing error detector (TED) or a phase detector to measure a sampling offset. The CR block can use the sampling offset to control sampling of subsequent data by the ADC. A jitter extraction block can use the sampling offset to re-sample the current data to obtain re-sampled data based on the sampling offset to remove jitter from the current data.
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公开(公告)号：US20240039711A1
公开(公告)日：2024-02-01
申请号：US17878464
申请日：2022-08-01
Applicant: Mellanox Technologies, Ltd.
Inventor： Tali Septon , Elad Mentovich , Yonatan Piasetzky , Moshe B. Oron , Isabelle Cestier
CPC classification number: H04L9/0855 , H04B10/70
Abstract: Bi-directional quantum interconnects are provided that include a first communication module and a second communication module. The first communication module includes a first quantum transmitter and a first quantum receiver, and the second communication module includes a second quantum transmitter and a second quantum receiver. The example interconnect further includes a first communication medium communicably coupling the first communication module and the second communication module such that communication is provided between the first quantum transmitter and the second quantum receiver and between the second quantum transmitter and the first quantum receiver via the first communication medium. The first quantum transmitter and the second quantum transmitter generate qubits having first and second quantum characteristics, respectively, to allow for bi-directional quantum communication over a common channel.
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公开(公告)号：US20240039627A1
公开(公告)日：2024-02-01
申请号：US17896877
申请日：2022-08-26
Applicant: Mellanox Technologies, Ltd.
Inventor： Paraskevas Bakopoulos , Konstantinos Tokas , Ioannis (Giannis) Patronas , Nikolaos Argyris , Dimitrios Syrivelis , Dimitrios Kalavrouziotis , Elad Mentovich , Eitan Zahavi , Louis Bennie Capps, JR. , Prethvi Ramesh Kashinkunti , Julie Irene Marcelle Bernauer
IPC: H04B10/073 , H04B10/077 , H04B10/079
CPC classification number: H04B10/073 , H04B10/0771 , H04B10/0773 , H04B10/0791
Abstract: Systems, computer program products, and methods are described herein for network discovery, port identification, and/or identifying fiber link failures in an optical network, in accordance with an embodiment of the invention. The present invention may be configured to sequentially connect each port of an optical switch to a network port of a server and generate, based on information associated with network devices connected to the ports, a network map. The network map may identify which network devices are connected to which ports of the optical switch and may permit dynamic port mapping for network installation, upgrades, repairs, and/or the like. The present invention may also be configured to determine a fiber link in which a failure occurred and reconfigure the optical switch to allow communication between an optical time-domain reflectometer and the fiber link to test the fiber link.
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Patent Agency Ranking
86.发明公开公开(公告)号：US20240028534A1
公开(公告)日：2024-01-25
申请号：US17874802
申请日：2022-07-27
Applicant: MELLANOX TECHNOLOGIES, LTD.
CPC classification number: G06F13/28 , G06F13/1673
Abstract: A high performance mechanism for exporting peripheral services and offloads using Direct Memory Access (DMA) engine is presented. The DMA engine comprises a ring buffer, a DMA memory, and a DMA engine interface operatively coupled to the ring buffer and the DMA memory. The DMA engine interface is configured to retrieve, from the ring buffer, a first DMA request; extract first transfer instructions from the first DMA request; retrieve a first data corresponding to the first DMA request from the DMA memory; and execute the first DMA request using the first data based on at least the first transfer instructions.
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公开(公告)号：US11876885B2
公开(公告)日：2024-01-16
申请号：US17335122
申请日：2021-06-01
Applicant: MELLANOX TECHNOLOGIES, LTD.
Inventor： Dotan David Levi , Ariel Shahar , Shahaf Shuler , Ariel Almog , Eitan Hirshberg , Natan Manevich
IPC: H04L7/00
CPC classification number: H04L7/0091
Abstract: A timing system including timing circuitry which includes an arming queue, a clock work queue, and a clock completion queue. At least the clock work queue is to provide timing information, and the arming queue is to arm the clock work queue. Related apparatus and methods are also provided.
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公开(公告)号：US20240015419A1
公开(公告)日：2024-01-11
申请号：US17869932
申请日：2022-07-21
Applicant: Mellanox Technologies, Ltd.
Inventor： Ioannis (Giannis) Patronas , Dotan David Levi , Wojciech Wasko , Paraskevas Bakopoulos , Dimitrios Syrivelis , Elad Mentovich
IPC: H04Q11/00 , H04B10/2575
CPC classification number: H04Q11/0005 , H04B10/25753 , H04Q2011/0045 , H04Q2011/005
Abstract: Network devices and associated methods are provided for synchronization in an optically switched network. The network device includes one or more ports in communication with a plurality of devices via an optical switch. The one or more ports receive a master clock signal having a first frequency from a first device of the plurality of devices. The network device includes a local clock in communication with the one or more ports and operating at a second frequency. The network device includes a synchronization manager in communication with the one or more ports and the local clock and configured to be enabled and disabled. When the synchronization manager is enabled, it receives the master clock signal via the one or more ports and transmits an instruction to the local clock to operate at the first frequency.
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公开(公告)号：US20240015130A1
公开(公告)日：2024-01-11
申请号：US17859022
申请日：2022-07-07
Applicant: MELLANOX TECHNOLOGIES, LTD.
Inventor： Eitan Zahavi , Guy Rozenberg , Matty Kadosh , Lion Levi , Boris Pismenny , Alex Netes , Miriam Menes , Lior Hodaya Bezen , Michael Tahar
IPC: H04L61/106 , H04L61/5092 , H04L61/5061
CPC classification number: H04L61/106 , H04L61/5092 , H04L61/5061
Abstract: A method for communication includes provisioning each node in a network with a respective set of two or more network addresses. Each node in succession is assigned a respective network address from the respective provisioned set that has not been assigned for use by any preceding node. Upon finding for a given node that all the network addresses in the respective provisioned set were assigned to preceding nodes, the preceding nodes are searched to identify a candidate node having an additional network address in the respective provisioned set, other than the assigned respective network address, that was not yet assigned to any of the nodes. The additional network address is assigned to the candidate node instead of the respective network address that was previously assigned to the candidate node, and the assigning of the network addresses to the nodes in the succession resumes following the candidate node.
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公开(公告)号：US20230421418A1
公开(公告)日：2023-12-28
申请号：US17850406
申请日：2022-06-27
Applicant: Mellanox Technologies, Ltd.
Inventor： Oz Harel , Hananel Faig , Yair Yakoby
CPC classification number: H04L25/03987 , H04L27/01 , H04L1/0054 , H04L1/203
Abstract: A receiver including an equalization component to receive a signal comprising a sequence of samples corresponding to symbols and generate an equalized signal with an estimated sequence of symbols corresponding to the signal. The receiver further includes a decision generation component to receive the equalized signal and generate, based on the equalized signal, a decision comprising a sequence of one or more bits that represent each symbol of the sequence of symbols and a confidence level corresponding to the decision.
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