公开(公告)号：US08687418B1

公开(公告)日：2014-04-01

申请号：US12623369

申请日：2009-11-20

Applicant: Rajiv Yadav Ranjan ,  Ebrahim Abedifard ,  Petro Estakhri ,  Parviz Keshtbod

Inventor： Rajiv Yadav Ranjan ,  Ebrahim Abedifard ,  Petro Estakhri ,  Parviz Keshtbod

IPC: G11C11/34

CPC classification number: H01F41/303 ,  B82Y10/00 ,  B82Y25/00 ,  B82Y40/00 ,  G11C11/161 ,  H01F10/3236 ,  H01F10/3254 ,  H01F10/3272 ,  H01L21/28273 ,  H01L27/11521 ,  H01L27/11524 ,  H01L29/42332 ,  H01L29/7881

Abstract: An embodiment of the present invention includes a non-volatile storage unit comprising a first and second N-diffusion well separated by a distance of P-substrate. A first isolation layer is formed upon the first and second N-diffusion wells and the P-substrate. A nano-pillar charge trap layer is formed upon the first isolation layer and includes conductive nano-pillars interspersed between non-conducting regions. The storage unit further includes a second isolation layer formed upon the nano-pillar charge trap layer; and at least one word line formed upon the second isolation layer and above a region of nano-pillar charge trap layer. The nano-pillar charge trap layer is operative to trap charge upon application of a threshold voltage. Subsequently, the charge trap layer may be read to determine any charge stored in the non-volatile storage unit, where presence or absence of stored charge in the charge trap layer corresponds to a bit value.

Abstract translation: 本发明的实施例包括非易失性存储单元，其包括以P基底间隔开的第一和第二N-扩散阱。 在第一和第二N-扩散阱和P-基底上形成第一隔离层。 纳米柱电荷陷阱层形成在第一隔离层上，并且包括散布在非导电区域之间的导电纳米柱。 存储单元还包括形成在纳米柱电荷陷阱层上的第二隔离层; 以及形成在第二隔离层上方和纳米柱电荷陷阱层的区域上方的至少一个字线。 纳米柱电荷陷阱层可用于在施加阈值电压时捕获电荷。 随后，可以读取电荷陷阱层以确定存储在非易失性存储单元中的任何电荷，其中电荷陷阱层中存在或不存在电荷对应于位值。

公开(公告)号：US20140050009A1

公开(公告)日：2014-02-20

申请号：US13585774

申请日：2012-08-14

Applicant: Ebrahim Abedifard ,  Parviz Keshtbod

Inventor： Ebrahim Abedifard ,  Parviz Keshtbod

IPC: G11C11/02 ,  G11C11/21

CPC classification number: G11C11/1673 ,  G11C8/16 ,  G11C11/16 ,  G11C11/1657 ,  G11C11/1659 ,  G11C11/1675

Abstract: A memory array is organized into rows and columns of resistive elements and is disclosed to include a resistive element to be read or to be written thereto. Further, a first access transistor is coupled to the resistive element and to a first source line and a second access transistor is coupled to the resistive element and to a second source line, the resistive element being coupled at one end to the first and second access transistors and at an opposite end to a bit line. The memory array further has other resistive elements that are each coupled to the bit line. The resistive element is written to while one or more of the other resistive elements are being read.

公开(公告)号：US20130267042A1

公开(公告)日：2013-10-10

申请号：US13443818

申请日：2012-04-10

Applicant: Kimihiro Satoh ,  Yiming Huai ,  Yuchen Zhou ,  Jing Zhang ,  Dong Ha Jung ,  Ebrahim Abedifard ,  Rajiv Yadav Ranjan ,  Parviz Keshtbod

Inventor： Kimihiro Satoh ,  Yiming Huai ,  Yuchen Zhou ,  Jing Zhang ,  Dong Ha Jung ,  Ebrahim Abedifard ,  Rajiv Yadav Ranjan ,  Parviz Keshtbod

IPC: H01L21/02

CPC classification number: H01L27/222 ,  H01L43/12

Abstract: Fabrication methods for MRAM are described wherein any re-deposited metal on the sidewalls of the memory element pillars is cleaned before the interconnection process is begun. In embodiments the pillars are first fabricated, then a dielectric material is deposited on the pillars over the re-deposited metal on the sidewalls. The dielectric material substantially covers any exposed metal and therefore reduces sources of re-deposition during subsequent etching. Etching is then performed to remove the dielectric material from the top electrode and the sidewalls of the pillars down to at least the bottom edge of the barrier. The result is that the previously re-deposited metal that could result in an electrical short on the sidewalls of the barrier is removed. Various embodiments of the invention include ways of enhancing or optimizing the process. The bitline interconnection process proceeds after the sidewalls have been etched clean as described.

Abstract translation: 描述了用于MRAM的制造方法，其中在互连过程开始之前清洁存储元件柱的侧壁上的任何重新沉积的金属。 在实施例中，首先制造柱，然后将介电材料沉积在侧壁上的再沉积金属上的柱上。 电介质材料基本上覆盖任何暴露的金属，因此在随后的蚀刻期间减少再沉积的来源。 然后进行蚀刻以将电介质材料从顶部电极和柱的侧壁向下移动到至少阻挡层的底部边缘。 结果是可能导致在屏障的侧壁上导致电短路的先前重新沉积的金属被去除。 本发明的各种实施方案包括增强或优化方法的方法。 如所描述的那样，在侧壁被蚀刻清洁之后，进行位线互连处理。

公开(公告)号：US08542524B2

公开(公告)日：2013-09-24

申请号：US12975304

申请日：2010-12-21

Applicant: Parviz Keshtbod ,  Roger Klas Malmhall ,  Rajiv Yadav Ranjan

Inventor： Parviz Keshtbod ,  Roger Klas Malmhall ,  Rajiv Yadav Ranjan

IPC: G11C11/00

CPC classification number: H01L43/12 ,  B82Y10/00 ,  G11C11/161 ,  H01L27/228 ,  H01L43/08

Abstract: A method of making a magnetic random access memory cell includes forming a magnetic tunnel junction (MTJ) on top of a wafer, depositing oxide on top of the MTJ, depositing a photo-resist layer on top of the oxide layer, forming a trench in the photo-resist layer and oxide layer where the trench has a width that is substantially the same as that of the MTJ. Then, the photo-resist layer is removed and a hard mask layer is deposited on top of the oxide layer in the trench and the wafer is planarized to remove the portion of the hard mask layer that is not in the trench to substantially level the top of oxide layer and the hard layer on the wafer. The remaining oxide layer is etched and the MTJ is etched to remove the portion of the MTJ which is not covered by the hard mask layer.

公开(公告)号：US08508984B2

公开(公告)日：2013-08-13

申请号：US12040801

申请日：2008-02-29

Applicant: Rajiv Yadav Ranjan ,  Parviz Keshtbod ,  Roger Klas Malmhall

Inventor： Rajiv Yadav Ranjan ,  Parviz Keshtbod ,  Roger Klas Malmhall

IPC: G11C11/00

CPC classification number: H01L43/12 ,  G11C11/161 ,  G11C11/1673 ,  G11C11/1675 ,  G11C11/5607 ,  H01L43/08

Abstract: A non-volatile magnetic memory element includes a fixed layer, a barrier layer formed on top of the fixed layer, and a free layer formed on top of the barrier layer, wherein the electrical resistivity of the barrier layer is reduced by placing said barrier layer under compressive stress. Compressive stress is induced by either using a compressive stress inducing layer, or by using inert gases at low pressure during the sputtering process as the barrier layer is deposited, or by introducing compressive stress inducing molecules into the molecular lattice of the barrier layer.

Abstract translation: 非易失性磁存储元件包括固定层，形成在固定层顶部上的阻挡层和形成在阻挡层顶部上的自由层，其中阻挡层的电阻率通过将阻挡层 在压应力下。 或者通过使用压缩应力诱导层或在溅射过程中使用惰性气体在溅射过程中作为阻挡层被沉积或通过将压应力诱导分子引入到阻挡层的分子晶格中而引起压缩应力。

公开(公告)号：US08440471B2

公开(公告)日：2013-05-14

申请号：US13345608

申请日：2012-01-06

Applicant: Rajiv Yadav Ranjan ,  Parviz Keshtbod ,  Mahmud Assar

Inventor： Rajiv Yadav Ranjan ,  Parviz Keshtbod ,  Mahmud Assar

IPC: H01L21/00 ,  H01L29/82 ,  G01C11/02

CPC classification number: G06F12/0246 ,  G11C11/15 ,  G11C11/161 ,  G11C11/1659 ,  G11C11/1675 ,  G11C14/00 ,  H01L27/105 ,  H01L27/224

Abstract: A method of flash-RAM memory includes non-volatile random access memory (RAM) formed on a monolithic die and non-volatile page-mode memory formed on top of the non-volatile RAM, the non-volatile page-mode memory and the non-volatile RAM reside on the monolithic die. The non-volatile RAM is formed of stacks of magnetic memory cells arranged in three-dimensional form for higher density and lower costs.

Abstract translation: 闪存RAM存储器的方法包括形成在单片模块上的非易失性随机存取存储器（RAM）和形成在非易失性RAM，非易失性页面模式存储器和非易失性页面模式存储器之上的非易失性页面模式存储器 非易失性RAM驻留在单片模具上。 非易失性RAM由以三维形式布置的磁存储单元堆叠形成，用于更高密度和更低成本。

公开(公告)号：US08427863B2

公开(公告)日：2013-04-23

申请号：US12986802

申请日：2011-01-07

Applicant: Rajiv Yadav Ranjan ,  Roger Klaus Malmhall ,  Parviz Keshtbod

Inventor： Rajiv Yadav Ranjan ,  Roger Klaus Malmhall ,  Parviz Keshtbod

IPC: G11C11/00

CPC classification number: G11C11/161 ,  G11C11/1655 ,  G11C11/1659 ,  G11C11/1673 ,  G11C11/1675 ,  G11C11/5607 ,  G11C19/0808 ,  H01L27/222 ,  H01L43/02 ,  H01L43/08

Abstract: A multi-state low-current-switching magnetic memory element (magnetic memory element) comprising a free layer, two stacks, and a magnetic tunneling junction is disclosed. The stacks and magnetic tunneling junction are disposed upon surfaces of the free layer, with the magnetic tunneling junction located between the stacks. The stacks pin magnetic domains within the free layer, creating a free layer domain wall. A current passed from stack to stack pushes the domain wall, repositioning the domain wall within the free layer. The position of the domain wall relative to the magnetic tunnel junction corresponds to a unique resistance value, and passing current from a stack to the magnetic tunnel junction reads the magnetic memory element's resistance. Thus, unique memory states may be achieved by moving the domain wall.

Abstract translation: 公开了一种包括自由层，两个堆叠和磁性隧道结的多态低电流切换磁存储元件（磁存储元件）。 堆叠和磁性隧道结设置在自由层的表面上，磁性隧道结位于堆叠之间。 堆叠在自由层内引导磁畴，产生自由层畴壁。 从堆栈传递到堆栈的电流推动域壁，重新定位自由层内的域壁。 畴壁相对于磁性隧道结的位置对应于唯一的电阻值，并且将电流从堆叠传递到磁性隧道结读取磁存储元件的电阻。 因此，可以通过移动域壁来实现唯一的记忆状态。

公开(公告)号：US20130052752A1

公开(公告)日：2013-02-28

申请号：US13199490

申请日：2011-08-30

Applicant: Kimihiro Satoh ,  Yiming Huai ,  Jing Zhang ,  Rajiv Yadav Ranjan ,  Parviz Keshtbod ,  Roger K. Malmhall

Inventor： Kimihiro Satoh ,  Yiming Huai ,  Jing Zhang ,  Rajiv Yadav Ranjan ,  Parviz Keshtbod ,  Roger K. Malmhall

IPC: H01L21/8246

CPC classification number: H01L43/12 ,  H01L29/00

Abstract: Various embodiments of the invention relate to etching processes used in fabrication of MTJ cells in an MRAM device. The various embodiments can be used in combination with each other. The first embodiment adds a hard mask buffer layer between a hard mask and a top electrode. The second embodiment uses a multilayered etching hard mask. The third embodiment uses a multilayered top electrode structure including a first Cu layer under a second layer such as Ta. The fourth embodiment is a two-phase etching process used for the bottom electrode to remove re-deposited material while maintaining a more vertical sidewall etching profile. In the first phase the bottom electrode layer is removed using carbonaceous reactive ion etching until the endpoint. In the second phase an inert gas and/or oxygen plasma is used to remove the polymer that was deposited during the previous etching processes.

Abstract translation: 本发明的各种实施例涉及用于制造MRAM装置中的MTJ电池的蚀刻工艺。 各种实施例可以彼此组合使用。 第一实施例在硬掩模和顶电极之间添加硬掩模缓冲层。 第二实施例使用多层蚀刻硬掩模。 第三实施例使用包括第二层如Ta之下的第一Cu层的多层顶电极结构。 第四实施例是用于底部电极去除再沉积材料同时保持更垂直侧壁蚀刻轮廓的两相蚀刻工艺。 在第一阶段中，使用碳质反应离子蚀刻去除底部电极层直到端点。 在第二阶段中，使用惰性气体和/或氧等离子体去除在先前蚀刻工艺期间沉积的聚合物。

公开(公告)号：US08385108B1

公开(公告)日：2013-02-26

申请号：US13429293

申请日：2012-03-23

Applicant: Ebrahim Abedifard ,  Siamack Nemazie ,  Parviz Keshtbod

Inventor： Ebrahim Abedifard ,  Siamack Nemazie ,  Parviz Keshtbod

IPC: G11C11/00

CPC classification number: G11C11/14 ,  G11C11/1657 ,  G11C11/1659 ,  G11C11/1673 ,  G11C11/1675 ,  G11C11/1697

Abstract: A method of method of writing to a magnetic memory cell includes selecting a magnetic memory cell of a magnetic memory array to be written to, the magnetic memory cell including a pair of MTJs, and setting a bit line (BL) coupled to the magnetic memory cell to a state that causes current to flow through the pair of MTJs in a manner that causes the direction of current flow through one of the MTJs of the pair of MTJs to be in a direction opposite to that of the other MTJ of the pair of MTJs.

Abstract translation: 写入磁存储单元的方法的方法包括选择要写入的磁存储器阵列的磁存储单元，磁存储单元包括一对MTJ，以及设置耦合到磁存储器的位线（BL） 电池导致电流流过该对MTJ的状态，使得电流流过该对MTJ的MTJ之一的电流的方向处于与该对MTJ的另一个MTJ的方向相反的方向 MTJs。

公开(公告)号：US08363457B2

公开(公告)日：2013-01-29

申请号：US12125866

申请日：2008-05-22

Applicant: Parviz Keshtbod

Inventor： Parviz Keshtbod

IPC: G11C11/00

CPC classification number: G11C11/16 ,  G11C11/1659 ,  G11C11/1673 ,  G11C11/1693

Abstract: A sensing circuit includes a sense amplifier circuit having a first and second nodes through which a magnetic memory element is sensed. A first current source is coupled to the first node a second current source is coupled to the second node. A reference magnetic memory element has a resistance associated therewith and is coupled to the first node, the reference magnetic memory element receives current from the first current source. At least one memory element, having a resistance associated therewith, is coupled to the second node and receives current from the second current source. Current from the first current source and current from the second current source are substantially the same. The logic state of the at least one memory element is sensed by a comparison of the resistance of the at least one memory element to the resistance of the reference magnetic memory element.

Abstract translation: 感测电路包括具有第一和第二节点的读出放大器电路，通过该第一和第二节点检测磁存储元件。 第一电流源耦合到第一节点，第二电流源耦合到第二节点。 参考磁存储元件具有与之相关联的电阻并且耦合到第一节点，参考磁存储元件从第一电流源接收电流。 具有与其相关联的电阻的至少一个存储元件耦合到第二节点并从第二电流源接收电流。 来自第一电流源的电流和来自第二电流源的电流基本相同。 通过比较至少一个存储元件的电阻与参考磁存储元件的电阻来感测至少一个存储元件的逻辑状态。