公开(公告)号：US09564496B2

公开(公告)日：2017-02-07

申请号：US14932349

申请日：2015-11-04

Applicant: Soitec

Inventor： Michel Bruel

IPC: H01L29/36 ,  H01L21/268 ,  H01L21/302 ,  H01L21/78 ,  H01L21/762 ,  H01L29/06

CPC classification number: H01L29/36 ,  H01L21/268 ,  H01L21/302 ,  H01L21/76254 ,  H01L21/7806 ,  H01L29/0684

Abstract: A substrate is treated by means of at least one pulse of a luminous flux of determined wavelength. The substrate comprises an embedded layer that absorbs the luminous flux independently of the temperature. The embedded layer is interleaved between a first treatment layer and a second treatment layer. The first treatment layer has a coefficient of absorption of luminous flux that is low at ambient temperature and rises as the temperature rises. The luminous flux may be applied in several places of a surface of the first layer to heat regions of the embedded layer and generate a propagating thermal front in the first layer opposite the heated regions of the embedded layer, which generate constraints within the second layer.

Abstract translation: 借助于确定波长的光通量的至少一个脉冲来处理衬底。 衬底包括独立于温度吸收光通量的嵌入层。 嵌入层在第一处理层和第二处理层之间交错。 第一处理层具有在环境温度下低的光通量吸收系数，随着温度升高而升高。 光通量可以施加在第一层的表面的几个位置以加热嵌入层的区域，并且在与嵌入层的加热区域相对的第一层中产生传播的热前沿，其在第二层内产生约束。

公开(公告)号：US20160372484A1

公开(公告)日：2016-12-22

申请号：US15176925

申请日：2016-06-08

Applicant: Soitec

Inventor： Bich-Yen Nguyen ,  Frederic Allibert ,  Christophe Maleville

IPC: H01L27/12 ,  H01L21/266 ,  H01L21/84 ,  H01L23/66

CPC classification number: H01L27/1203 ,  H01L21/26506 ,  H01L21/26533 ,  H01L21/266 ,  H01L21/84 ,  H01L23/66

Abstract: A method for manufacturing a high-resistivity semiconductor-on-insulator substrate comprising the steps of: a) forming a dielectric layer and a semiconductor layer over a high-resistivity substrate, such that the dielectric layer is arranged between the high-resistivity substrate and the semiconductor layer; b) forming a hard mask or resist over the semiconductor layer, wherein the hard mask or resist has at least one opening at a predetermined position; c) forming at least one doped region in the high-resistivity substrate by ion implantation of an impurity element through the at least one opening of the hard mask or resist, the semiconductor layer and the dielectric layer; d) removing the hard mask or resist; and e) forming a radiofrequency, RF, circuit in and/or on the semiconductor layer at least partially overlapping the at least one doped region in the high-resistivity substrate.

Abstract translation: 一种用于制造绝缘体上绝缘体上的高电阻半导体衬底的方法，包括以下步骤：a）在高电阻率衬底上形成电介质层和半导体层，使得电介质层布置在高电阻率衬底和 半导体层; b）在所述半导体层上形成硬掩模或抗蚀剂，其中所述硬掩模或抗蚀剂在预定位置具有至少一个开口; c）通过所述硬掩模或抗蚀剂，所述半导体层和所述电介质层的所述至少一个开口离子注入杂质元素，在所述高电阻率衬底中形成至少一个掺杂区域; d）去除硬掩模或抗蚀剂; 以及e）在所述半导体层中和/或之上形成至少部分地与所述高电阻率衬底中的所述至少一个掺杂区域重叠的射频RF电路。

公开(公告)号：US09511996B2

公开(公告)日：2016-12-06

申请号：US14416860

申请日：2013-07-08

Applicant: Soitec

Inventor： Mariam Sadaka ,  Bernard Aspar ,  Chrystelle Lagahe Blanchard

IPC: H01L27/14 ,  B81C1/00 ,  H03H9/10 ,  B81B7/00

CPC classification number: B81C1/00246 ,  B81B7/0006 ,  B81B2201/0271 ,  B81B2207/015 ,  B81C1/00238 ,  B81C2203/0735 ,  B81C2203/0792 ,  H03H9/10

Abstract: Methods are used to form semiconductor devices that include an integrated circuit and a microelectromechanical system (MEMS) device operatively coupled with the integrated circuit. At least a portion of an integrated circuit may be fabricated on a surface of a substrate, and a MEMS device may be formed over the at least a portion of the integrated circuit. The MEMS device may be operatively coupled with the integrated circuit. Semiconductor structures and electronic devices including such structures are formed using such methods.

Abstract translation: 方法用于形成半导体器件，其包括集成电路和与集成电路可操作地耦合的微机电系统（MEMS）器件。 可以在衬底的表面上制造集成电路的至少一部分，并且可以在集成电路的至少一部分上形成MEMS器件。 MEMS器件可以与集成电路可操作地耦合。 使用这种方法形成包括这种结构的半导体结构和电子器件。

公开(公告)号：US20160352287A1

公开(公告)日：2016-12-01

申请号：US15036037

申请日：2014-11-14

Applicant: SOITEC SOLAR GMBH

Inventor： Philippe Gastaldo ,  Mathieu Guilhem

IPC: H02S50/15 ,  H02S40/22 ,  H01L31/0687

CPC classification number: H02S50/15 ,  H01L31/0543 ,  H01L31/0687 ,  H02S40/22 ,  Y02E10/52

Abstract: The disclosure relates to a device and method for testing a concentrated photovoltaic module comprising a plurality of submodules, which comprises: light sources; and parabolic mirrors coupled with the light sources so as to reflect the light from each source in quasi-collimated light beams toward the module to be tested, perpendicular to the module. Each light source comprises: an optical system comprising two parallel lenses on either side of a diaphragm; a lamp on the optical axis of the system; a reflector arranged on the axis, on the side opposite the optical system relative to the lamp, and translatably movable along the axis; and a housing containing the optical system, the lamp and the reflector and including an outlet opening for the light beam on the axis.

Abstract translation: 本公开涉及一种用于测试包括多个子模块的集中光伏模块的装置和方法，其包括：光源; 以及与光源耦合的抛物面镜，以便将来自准准直光束的每个源的光反射到待测模块垂直于模块。 每个光源包括：光学系统，其在隔膜的任一侧上包括两个平行透镜; 系统光轴上的灯; 反射器，其布置在所述轴线上，相对于所述灯在所述光学系统相对的一侧上，并且可沿所述轴线平移地移动; 以及包含光学系统，灯和反射器并且包括用于光束在轴上的出口的壳体的壳体。

公开(公告)号：US09481566B2

公开(公告)日：2016-11-01

申请号：US14416825

申请日：2013-07-08

Applicant: Soitec

Inventor： Mariam Sadaka ,  Bernard Aspar ,  Chrystelle Lagahe Blanchard

IPC: H01L29/40 ,  B81B7/00 ,  B81C1/00 ,  H03H9/10

CPC classification number: B81B7/007 ,  B81B2201/0271 ,  B81B2207/012 ,  B81B2207/015 ,  B81C1/00238 ,  B81C1/00246 ,  B81C1/00301 ,  B81C2203/0735 ,  B81C2203/0792 ,  H01L2224/16 ,  H03H9/10

Abstract: Methods of forming semiconductor devices comprising integrated circuits and microelectromechanical system (MEMS) devices operatively coupled with the integrated circuits involve the formation of an electrically conductive via extending at least partially through a substrate from a first major surface of the substrate toward an opposing second major surface of the substrate, and the fabrication of at least a portion of an integrated circuit on the first major surface of the substrate. A MEMS device is provided on the second major surface of the substrate, and the MEMS device is operatively coupled with the integrated circuit using the at least one electrically conductive via. Structures and devices are fabricated using such methods.

Abstract translation: 形成包括集成电路的半导体器件和与集成电路可操作耦合的微机电系统（MEMS）器件的方法包括形成导电通孔，该导电通孔至少部分地穿过衬底，从衬底的第一主表面向相对的第二主表面延伸 的衬底，以及在衬底的第一主表面上制造集成电路的至少一部分。 MEMS器件设置在衬底的第二主表面上，并且MEMS器件使用至少一个导电通孔与集成电路操作耦合。 使用这种方法制造结构和装置。

公开(公告)号：US09396987B2

公开(公告)日：2016-07-19

申请号：US14369594

申请日：2012-12-21

Applicant: Soitec

Inventor： Oleg Kononchuk

IPC: H01L21/02 ,  H01L21/762 ,  H01L21/18 ,  H01L21/265 ,  H01L21/683

CPC classification number: H01L21/76254 ,  H01L21/187 ,  H01L21/265 ,  H01L21/6836

Abstract: The invention relates to a method for fabricating a substrate, comprising the steps of providing a donor substrate with at least one free surface, performing an ion implantation at a predetermined depth of the donor substrate to form an in-depth predetermined splitting area inside the donor substrate, and is characterized in providing a layer of an adhesive, in particular an adhesive paste, over the at least one free surface of the donor substrate. The invention further relates to a semiconductor structure comprising a semiconductor layer, and a layer of a ceramic-based and/or a graphite-based and/or a metal-based adhesive provided on one main side of the semiconductor layer.

Abstract translation: 本发明涉及一种用于制造衬底的方法，包括以下步骤：向供体衬底提供至少一个自由表面，在供体衬底的预定深度处进行离子注入，以在供体内形成深入的预定分裂区域 衬底，并且其特征在于在施主衬底的至少一个自由表面上提供粘合剂层，特别是粘合剂糊剂层。 本发明还涉及一种半导体结构，其包括半导体层，以及设置在半导体层的一个主侧上的基于陶瓷的和/或基于石墨的和/或金属基粘合剂层。

公开(公告)号：US20160163535A1

公开(公告)日：2016-06-09

申请号：US14957133

申请日：2015-12-02

Applicant: Soitec

Inventor： Vivien Renauld ,  Monique Lecomte

IPC: H01L21/02

CPC classification number: H01L21/0254 ,  H01L21/02373 ,  H01L21/02488 ,  H01L21/02694 ,  H01L21/2007 ,  H01L21/6835 ,  H01L21/76254 ,  H01L2221/68318 ,  H01L2221/6835 ,  H01L2221/68381

Abstract: A process for transferring a useful layer to a receiver substrate includes providing a donor substrate comprising an intermediate layer, a carrier substrate, and a useful layer. The intermediate layer is free of species liable to degas during a subsequent heat treatment, and is configured to become soft at a temperature. The receiver substrate and the donor substrate are assembled. An additional layer is provided between the receiver substrate and the carrier substrate that comprises chemical species that are susceptible to diffuse into the intermediate layer during the subsequent heat treatment so as to form a weak zone. The heat treatment is carried out on the receiver substrate and the donor substrate at a second temperature higher than the first temperature.

Abstract translation: 用于将有用层转移到接收器衬底的方法包括提供包括中间层，载体衬底和有用层的施主衬底。 中间层在随后的热处理期间不含易于脱气的物质，并且被配置为在温度下变软。 组装接收器基板和供体基板。 在接收器基板和载体基板之间提供了附加层，其包括在随后的热处理期间易于扩散到中间层中以形成弱区的化学物质。 在高于第一温度的第二温度下，在接收器基板和供体基板上进行热处理。

公开(公告)号：US20160148971A1

公开(公告)日：2016-05-26

申请号：US14899243

申请日：2014-06-16

Applicant: SOITEC

Inventor： Marcel BROEKAART ,  Laurent MARINIER

IPC: H01L27/146

CPC classification number: H01L27/14687 ,  H01L21/6835 ,  H01L21/78 ,  H01L25/50 ,  H01L27/14636 ,  H01L27/1464 ,  H01L2221/68363 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A process for transferring a buried circuit layer comprises taking a donor substrate comprising an internal etch stop zone and covered on its front side with a circuit layer, producing over the entire circumference of the donor substrate either a peripheral trench or a peripheral routing, this routing or trench being produced over a depth such that they pass entirely through the circuit layer and extend into the donor substrate, depositing on the circuit layer and on the routed side or on the walls of the trench a layer of an etch stop material that is selective with respect to etching of the circuit layer, without filling the trench, bonding a receiver substrate to the donor substrate, and thinning the donor substrate by etching its back side until reaching the etch stop zone so as to obtain the transfer of the buried circuit layer to the receiver substrate.

Abstract translation: 用于传送掩埋电路层的工艺包括取下包含内部蚀刻停止区的施主衬底，并在其前侧覆盖有电路层，在施主衬底的整个圆周上产生外围沟槽或外围路由，该布线 或沟槽在深度上产生，使得它们完全通过电路层并延伸到施主衬底中，在电路层上和在沟道侧或沟槽的壁上沉积有选择性的蚀刻停止材料层 关于电路层的蚀刻，而不填充沟槽，将接收器衬底接合到施主衬底，并且通过蚀刻其背面直到到达蚀刻停止区来稀释施主衬底，以获得掩埋电路层的传输 到接收器基板。

公开(公告)号：US20160141198A1

公开(公告)日：2016-05-19

申请号：US14938492

申请日：2015-11-11

Applicant: Soitec

Inventor： Marcel Broekaart

IPC: H01L21/683

CPC classification number: H01L21/6835 ,  H01L21/02002 ,  H01L21/185 ,  H01L21/7806 ,  H01L2221/68313 ,  H01L2221/68327 ,  H01L2221/6834 ,  H01L2221/68363

Abstract: The invention relates to a process for transferring an active layer to a final substrate using a temporary substrate, the active layer comprises a first side having a three-dimensional surface topology, the process comprising: a first step of bonding the first side of the active layer to one side of the temporary substrate; a second step of bonding a second side of the active layer to the final substrate; and a third step of separating the active layer and the temporary substrate; the process being characterized in that the side of the temporary substrate possesses a surface topology complementary to the surface topology of the first side of the active layer, so that the surface topology of the temporary substrate encapsulates the surface topology of the first side of the active layer in the bonding first step.

Abstract translation: 本发明涉及一种使用临时衬底将活性层转移到最终衬底的方法，所述活性层包括具有三维表面拓扑结构的第一侧，所述方法包括：将活性物质的第一面接合的第一步骤 层到临时衬底的一侧; 将有源层的第二面接合到最终基板的第二步骤; 以及分离有源层和临时衬底的第三步骤; 该方法的特征在于，临时衬底的侧面具有与有源层的第一侧的表面拓扑互补的表面拓扑，使得临时衬底的表面拓扑封装有源层的第一侧的表面拓扑结构 接合第一步中的层。

公开(公告)号：US09330958B2

公开(公告)日：2016-05-03

申请号：US14360124

申请日：2012-11-21

Applicant: Soitec

Inventor： Gweltaz Gaudin

IPC: H01L21/30 ,  H01L21/762 ,  H01L21/02 ,  H01L21/265 ,  H01L21/306 ,  H01L21/324

CPC classification number: H01L21/76251 ,  H01L21/02164 ,  H01L21/02238 ,  H01L21/02532 ,  H01L21/02592 ,  H01L21/02595 ,  H01L21/0262 ,  H01L21/02667 ,  H01L21/26513 ,  H01L21/30625 ,  H01L21/324 ,  H01L21/76254

Abstract: The invention relates to a process for fabricating a heterostructure comprising at least one thin layer and a carrier substrate made of a semiconductor, the process comprising: bonding a first substrate made of a single-crystal first material, the first substrate comprising a superficial layer made of a polycrystalline second material, to a second substrate so that a bonding interface is created between the polycrystalline layer and the second substrate; removing from the free surface of one of the substrates, called the donor substrate, a thickness thereof so that only a thin layer is preserved; generating a layer of amorphous semiconductor material between the first substrate and the bonding interface by amorphization of the layer of polycrystalline material; and crystallizing the layer of amorphous semiconductor material, the newly crystallized layer having the same orientation as the adjacent first substrate.

Abstract translation: 本发明涉及一种用于制造异质结构的方法，该方法包括由半导体制成的至少一个薄层和载体衬底，所述方法包括：将由单晶第一材料制成的第一衬底接合，所述第一衬底包括形成的表面层 多晶第二材料的第二基板，以便在所述多晶层和所述第二基板之间形成接合界面; 从称为供体基板的一个基板的自由表面去除其厚度，使得仅保留薄层; 通过所述多晶材料层的非晶化在所述第一基板和所述接合界面之间产生非晶半导体材料层; 并且使非晶半导体材料层结晶，所述新结晶层具有与相邻的第一衬底相同的取向。