公开(公告)号：US20240331767A1

公开(公告)日：2024-10-03

申请号：US18614460

申请日：2024-03-22

Applicant: STMicroelectronics International N.V.

Inventor： Praveen Kumar VERMA ,  Anuj DHILLON

IPC: G11C11/419 ,  G11C11/418

CPC classification number: G11C11/419 ,  G11C11/418

Abstract: The present disclosure is directed to a device and method for accurately estimating a write self-time of a memory array. The write self-time is estimated by performing a simulated write operation on a write self-time bit cell having the same structure and arrangement as each of the bit cells of the memory array. The write operations on the bit cells of the memory array are stopped in response to detecting completion of the simulated write operation.

公开(公告)号：US20240330153A1

公开(公告)日：2024-10-03

申请号：US18602977

申请日：2024-03-12

Applicant: STMICROELECTRONICS INTERNATIONAL N.V.

Inventor： Alessandro BASTONI

IPC: G06F11/36

CPC classification number: G06F11/3636

Abstract: Method for monitoring the execution of an application software implementing a safety function, comprising implementing a software-based lock step on a dual asymmetrical processing units structure, the processing units structure including a first processing unit and a second processing unit having, due to the asymmetry, a different hardware structure and/or lower computations capability with respect to the first processing unit. A first runtime software is executed on the first processor while a second runtime software being a potentially modified version of the first runtime software and having the same behavior as that of the first runtime software, is executed on the second processor.

公开(公告)号：US20240329098A1

公开(公告)日：2024-10-03

申请号：US18615233

申请日：2024-03-25

Applicant: STMicroelectronics International N.V.

Inventor： Roberto TIZIANI ,  Francesca DE VITI

IPC: G01R15/20 ,  G01R19/00 ,  H01L21/8234 ,  H01L23/31

CPC classification number: G01R15/207 ,  G01R15/202 ,  G01R19/0092 ,  H01L21/8234 ,  H01L23/3121

Abstract: An insulating encapsulation encapsulates a semiconductor die having an integrated Hall current sensor configured to measure an electric current flowing adjacent an active surface of the semiconductor die. An electrically conductive trace is embedded in the insulating encapsulation. First electrically conductive formations extend through the insulating encapsulation towards opposed ends of the electrically conductive trace. The first electrically conductive formations are configured to cause an electrical current subject to measurement to flow in a current flow path through the electrically conductive trace. Second electrically conductive formations extend through the insulating encapsulation towards the active surface of the semiconductor die. The second electrically conductive formations are configured to activate the Hall current sensor integrated in the semiconductor die.

公开(公告)号：US12107486B2

公开(公告)日：2024-10-01

申请号：US18234137

申请日：2023-08-15

Applicant: STMicroelectronics International N.V.

Inventor： Akshat Jain

IPC: H02M1/08 ,  H02M1/32 ,  H03K17/082 ,  H05B6/10 ,  H02M7/04

CPC classification number: H02M1/08 ,  H02M1/32 ,  H03K17/0828 ,  H05B6/108 ,  H02M7/04

Abstract: Methods of operating an induction geyser include drawing current through a resonant tank via a transistor, generating a changing magnetic field around the resonant tank. Owing to the strategic placement of the resonant tank in proximity to a fluid tank, the changing magnetic field envelopes the fluid tank. In a first method, the voltage across the transistor's conduction terminals is monitored, and when this voltage surpasses a predefined threshold, indicating an overvoltage condition, a corrective action is initiated in which a gate driver pulls up a gate drive signal that drives the transistor. In a second method, the current flowing between the transistor's conduction terminals is monitored, and upon detecting an overcurrent condition where the current exceeds a set threshold the gate driver is activated to pull down the gate drive signal. Both methods aim to keep operation of the geyser within desired parameters.

公开(公告)号：US20240321795A1

公开(公告)日：2024-09-26

申请号：US18603113

申请日：2024-03-12

Applicant: STMicroelectronics International N.V.

Inventor： Olivier ORY ,  Michael DE CRUZ

IPC: H01L23/00 ,  H01L21/288 ,  H01L21/463 ,  H01L21/768 ,  H05K1/18

CPC classification number: H01L24/13 ,  H01L21/288 ,  H01L21/463 ,  H01L21/76865 ,  H01L24/29 ,  H01L24/73 ,  H05K1/181 ,  H01L2224/13007 ,  H01L2224/13025 ,  H01L2224/29005 ,  H01L2224/2919 ,  H01L2224/73153 ,  H01L2924/01029

Abstract: The present disclosure relates to a method of manufacturing first electronic components, each comprising a second electronic component, each second component comprising at least two contact metallizations, the method comprising: a) forming, on a substrate, at least two metal pillars; b) forming, over a portion of the surface of each pillar, a metallization of the component; c) covering the surface of the substrate, the pillars, and the metallizations of the first components with a first resin layer; d) removing the substrate to expose a surface of the pillars, opposite to the metallizations of the components; e) bonding and electrically connecting the second components, by their metallizations, to the surface of the pillars opposite to the metallizations of the first components; and f) expose the surface of the metallizations of the first components opposite to the pillars.

公开(公告)号：US20240320086A1

公开(公告)日：2024-09-26

申请号：US18612421

申请日：2024-03-21

Applicant: STMicroelectronics International N.V.

Inventor： Pierre-Alexandre BLANC ,  Gilles VAN ASSCHE

IPC: G06F11/10 ,  G06F21/60

CPC classification number: G06F11/1004 ,  G06F11/1068 ,  G06F21/602

Abstract: The present description concerns a method of checking a first data element, executed by an electronic device comprising a processor and a memory, wherein said first data element is not stored in said memory and is divided in N second data elements independent from the first data element, each second data element being stored in said memory, and a result of an application of a XOR function to the N second elements being equal to the first data element, wherein an image of the first data element by a CRC function linear with respect to the XOR function is stored in said memory, and said method comprising a step, executed by said processor, of checking if said image of the first data element by said CRC function is equal to an application of the XOR function to the images of N second elements by said CRC function.

公开(公告)号：US12093193B2

公开(公告)日：2024-09-17

申请号：US17067967

申请日：2020-10-12

Applicant: STMicroelectronics International N.V.

Inventor： Ankur Bal ,  Rupesh Singh

IPC: G06F13/16 ,  G06F7/487 ,  G06F9/30 ,  G06F17/16

CPC classification number: G06F13/1668 ,  G06F7/4876 ,  G06F9/3001 ,  G06F9/30021 ,  G06F17/16

Abstract: Individual bits of a K bit unary data word, wherein K is greater than one, are applied to K polyphase finite impulse response filter circuits. Each polyphase finite impulse response filter circuit receives a different bit and operates with a single bit precision to generate from each received bit a filtered output data word. A gain adjustment is applied by a gain stage circuit to each filtered output data word to generate a corresponding gain adjusted output data word. The gain adjusted output data words from the gain stage circuits are summed to generate an output data word. The unary data word may be output from a source such as a data encoder or a quantizer.

公开(公告)号：US20240304713A1

公开(公告)日：2024-09-12

申请号：US18591344

申请日：2024-02-29

Applicant: STMicroelectronics International N.V.

Inventor： Ferdinando IUCOLANO ,  Aurore CONSTANT ,  Cristina TRINGALI ,  Maria Eloisa CASTAGNA

IPC: H01L29/778 ,  H01L29/20 ,  H01L29/40 ,  H01L29/66

CPC classification number: H01L29/7786 ,  H01L29/2003 ,  H01L29/402 ,  H01L29/66462

Abstract: An HEMT device is formed on a semiconductor body having a semiconductive heterostructure. A control region of a semiconductor material, is arranged on the semiconductor body and has a top surface and lateral sides. A control terminal, of conductive material, extends on and in contact with the top surface of the control region. A passivation layer of non-conductive material, extends on the semiconductor body, partially on the top surface of the control region and on the lateral sides of the control region, laterally and at a distance from the control terminal.

公开(公告)号：US20240302219A1

公开(公告)日：2024-09-12

申请号：US18182058

申请日：2023-03-10

Applicant: STMicroelectronics International N.V.

Inventor： Federico VERCESI ,  Silvia NICOLI ,  Cinzia DE MARCO

IPC: G01K7/01 ,  H01L23/485 ,  H01L23/522

CPC classification number: G01K7/015 ,  H01L23/485 ,  H01L23/5226

Abstract: Disclosed herein are thermal sensor devices including TMOS devices with a mass suspended over a cavity by springs extending between a frame and the mass. The thermal sensor devices include stoppers that limit upward and/or downward movement of the springs and therefore the mass. These stoppers are formed from sidewalls supporting a top cap over the frame, springs, and mass. The stoppers are constructed by using various overlapping metal layers during fabrication. Details of forming the stoppers using these overlapping metal layers are contained here.

公开(公告)号：US20240297249A1

公开(公告)日：2024-09-05

申请号：US18583748

申请日：2024-02-21

Applicant: STMicroelectronics International N.V.

Inventor： Alfio GUARNERA ,  Mario Giuseppe SAGGIO ,  Cateno Marco CAMALLERI ,  Edoardo ZANETTI

IPC: H01L29/78 ,  H01L21/04 ,  H01L29/06 ,  H01L29/16

CPC classification number: H01L29/7811 ,  H01L21/0465 ,  H01L29/0603 ,  H01L29/1608

Abstract: Method of manufacturing an electronic device, comprising the steps of: arranging a semiconductor body of N-type, having a lattice structure with spatial symmetry, comprising an active area an edge region surrounding the active area; forming, in the edge region, an intentionally damaged region wherein the lattice structure has no spatial symmetry; forming an edge termination region of P-type at the damaged region, by random implant; forming a current spreading layer, CSL, in the edge region at and lateral to the damaged region, by channeled implant. The CSL has, at the damaged region, a minimum thickness and, laterally to the damaged region, a maximum thickness. The minimum thickness is lower than the thickness of the edge termination region.