公开(公告)号：US4751142A

公开(公告)日：1988-06-14

申请号：US908272

申请日：1986-09-17

Applicant: Hisao Arimune ,  Mitsuo Miyazaki ,  Takashi Maeda

Inventor： Hisao Arimune ,  Mitsuo Miyazaki ,  Takashi Maeda

IPC: G11B11/105 ,  G11B7/24

CPC classification number: G11B11/10586 ,  Y10S428/90 ,  Y10T428/265

Abstract: Disclosed is a magneto-optical recording element comprising a magnetic film composed of an alloy having a composition represented by the following formula:(Gd.sub.y Dy.sub.1-y).sub.x Fe.sub.1-x (0.15.ltoreq.x.ltoreq.0.35 and 0.30.ltoreq.y.ltoreq.0.95)This magnetic film is characterized in that the nuclear magnetic field, coercive force and saturation magnetic filed in the Kerr hysteresis loop are substantially same at temperatures higher than 100.degree. C.

Abstract translation: 公开了一种磁光记录元件，其包括由具有由下式表示的组成的合金构成的磁性膜：（GdyDy1-y）xFe1-x（0.15≤x≤0.35和0.30

公开(公告)号：US08853766B2

公开(公告)日：2014-10-07

申请号：US13275436

申请日：2011-10-18

Applicant: Takashi Maeda ,  Yoshihisa Iwata

Inventor： Takashi Maeda ,  Yoshihisa Iwata

IPC: H01L29/792 ,  H01L27/115

CPC classification number: H01L23/528 ,  H01L23/5226 ,  H01L27/11551 ,  H01L27/11556 ,  H01L27/1157 ,  H01L27/11578 ,  H01L27/11582 ,  H01L2924/0002 ,  H01L2924/00

Abstract: In a nonvolatile semiconductor memory device, a stacked body is formed by alternately stacking dielectric films and conductive films on a silicon substrate and a plurality of through holes extending in the stacking direction are formed in a matrix configuration. A shunt interconnect and a bit interconnect are provided above the stacked body. Conductor pillars are buried inside the through holes arranged in a line immediately below the shunt interconnect out of the plurality of through holes, and semiconductor pillars are buried inside the remaining through holes. The conductive pillars are formed from a metal, or low resistance silicon. Its upper end portion is connected to the shunt interconnect and its lower end portion is connected to a cell source formed in an upper layer portion of the silicon substrate.

Abstract translation: 在非易失性半导体存储器件中，通过在硅衬底上交替堆叠电介质膜和导电膜来形成层叠体，并且以矩阵形式形成沿堆叠方向延伸的多个通孔。 分路互连和位互连设置在堆叠体的上方。 导体支柱埋设在多个通孔中的分流互连的正下方配置的贯通孔的内侧，半导体柱埋设在剩余通孔的内部。 导电柱由金属或低电阻硅形成。 其上端部连接到分路互连，并且其下端部连接到形成在硅衬底的上层部分中的电池源。

公开(公告)号：US20140063518A1

公开(公告)日：2014-03-06

申请号：US14015153

申请日：2013-08-30

Applicant: Takashi MAEDA

Inventor： Takashi MAEDA

IPC: H04N1/00 ,  G06K15/16

CPC classification number: H04N1/00591 ,  B65H29/00 ,  B65H43/00 ,  B65H2511/20 ,  B65H2557/23 ,  B65H2801/39 ,  G06K15/16 ,  H04N1/00657 ,  H04N1/32667 ,  H04N2201/0081 ,  B65H2220/03

Abstract: A sheet conveying device includes: a conveying unit; a nonvolatile memory; and a controller. The conveying unit is configured to convey a sheet along a conveying path. The controller is configured to control the conveying unit to convey the sheet, store position data in the nonvolatile memory during conveyance of the sheet, determine whether or not the sheet conveying device is started, and drive the conveying unit for an amount determined by the position data if the sheet conveying device is started. The conveying path is divided into a plurality of segments. The position data identifies a segment in which the sheet stays. The more downstream the segment identified by the position data is in the conveying path, the smaller the amount determined by the position data is.

Abstract translation: 纸张输送装置包括：输送单元; 非易失性存储器 和控制器。 输送单元构造成沿输送路径输送纸张。 控制器被配置为控制传送单元传送片材，在片材的传送期间将位置数据存储在非易失性存储器中，确定片材传送装置是否启动，并且将传送单元驱动由位置确定的量 数据如果纸张传送装置启动。 输送路径被分成多个段。 位置数据表示纸张停留在哪一段。 通过位置数据识别的段的下游越靠近传送路径，位置数据确定的量越小。

公开(公告)号：US08623530B2

公开(公告)日：2014-01-07

申请号：US13542907

申请日：2012-07-06

Applicant: Kouji Kitsunai ,  Takashi Maeda

Inventor： Kouji Kitsunai ,  Takashi Maeda

IPC: G11B5/73

CPC classification number: G11B5/7315 ,  G11B5/82

Abstract: A glass substrate for a magnetic disk, wherein, in regions with respect to two places arbitrarily selected on a surface of the glass substrate on its central portion side relative to its outer peripheral end, a surface shape with a shape wavelength in a band of 60 to 500 μm is extracted from surface shapes in each of the regions and, assuming that a root mean square roughness Rq of the surface shape is given as a microwaviness Rq, the difference between the microwavinesses Rq of the regions is 0.02 nm or less or the difference between standard deviations of the microwavinesses Rq of the regions is 0.04 nm or less.

Abstract translation: 一种磁盘用玻璃基板，其特征在于，在相对于其外周端部的中央部侧的玻璃基板的表面上任意选择的两个位置的区域中，形状波长为60nm的波长的表面形状 在每个区域中从表面形状提取至500μm，并且假定表面形状的均方根粗糙度Rq作为微波特性Rq，区域的微波特性Rq之差为0.02nm以下，或者 区域的微波的标准偏差之间的差异为0.04nm以下。

公开(公告)号：US20120242505A1

公开(公告)日：2012-09-27

申请号：US13514112

申请日：2010-03-16

Applicant: Takashi Maeda ,  Shigeki Morita

Inventor： Takashi Maeda ,  Shigeki Morita

IPC: G08G1/0967

CPC classification number: G08G1/164 ,  G08G1/096783

Abstract: When a decision is made that it is necessary to call driver's attention as a result of analyzing driving safety support information received by a roadside device information receiving unit 34 and vehicle driving state information detected by a vehicle state detecting unit 33, an attention-calling screen, in which a target detection area including an obstacle is superimposed upon a corresponding map information, is displayed.

Abstract translation: 作为通过分析由路侧设备信息接收单元34接收的驾驶安全性支持信息和由车辆状态检测单元33检测到的车辆行驶状态信息来决定需要呼叫驾驶员的注意事项的关注呼叫屏幕 ，其中包括障碍物的目标检测区域叠加在相应的地图信息上。

公开(公告)号：US20120218821A1

公开(公告)日：2012-08-30

申请号：US13463889

申请日：2012-05-04

Applicant: Kiyotaro ITAGAKI ,  Yoshihisa IWATA ,  Hiroyasu TANAKA ,  Masaru KIDOH ,  Masaru KITO ,  Ryota KATSUMATA ,  Hideaki AOCHI ,  Akihiro NITAYAMA ,  Takashi MAEDA ,  Tomoo HISHIDA

Inventor： Kiyotaro ITAGAKI ,  Yoshihisa IWATA ,  Hiroyasu TANAKA ,  Masaru KIDOH ,  Masaru KITO ,  Ryota KATSUMATA ,  Hideaki AOCHI ,  Akihiro NITAYAMA ,  Takashi MAEDA ,  Tomoo HISHIDA

IPC: G11C16/04

CPC classification number: G11C16/0483 ,  G11C16/08 ,  G11C16/16 ,  G11C16/26 ,  G11C16/30

Abstract: A non-volatile semiconductor storage device includes: a memory string including a plurality of memory cells connected in series; a first selection transistor having one end connected to one end of the memory string; a first wiring having one end connected to the other end of the first selection transistor; a second wiring connected to a gate of the first selection transistor. A control circuit is configured to boost voltages of the second wiring and the first wiring in the erase operation, while keeping the voltage of the first wiring greater than the voltage of the second wiring by a certain potential difference. The certain potential difference is a potential difference that causes a GIDL current.

Abstract translation: 非易失性半导体存储装置包括：包括串联连接的多个存储单元的存储串; 第一选择晶体管，其一端连接到存储器串的一端; 第一布线，其一端连接到第一选择晶体管的另一端; 连接到第一选择晶体管的栅极的第二布线。 控制电路被配置为在保持第一布线的电压大于第二布线的电压一定电位差的同时，在擦除操作中提高第二布线和第一布线的电压。 一定的电位差是导致GIDL电流的电位差。

公开(公告)号：US08233323B2

公开(公告)日：2012-07-31

申请号：US12694690

申请日：2010-01-27

Applicant: Tomoo Hishida ,  Yoshihisa Iwata ,  Kiyotaro Itagaki ,  Takashi Maeda

Inventor： Tomoo Hishida ,  Yoshihisa Iwata ,  Kiyotaro Itagaki ,  Takashi Maeda

IPC: G11C16/04

CPC classification number: G11C8/08 ,  G11C16/0483 ,  G11C16/08 ,  G11C16/10 ,  G11C16/14 ,  G11C16/3454 ,  H01L27/11573 ,  H01L27/11578 ,  H01L27/11582

Abstract: A non-volatile semiconductor storage device includes a control circuit performing an erase operation to erase data from a selected one of memory transistors. The control circuit applies a first voltage to the other end of selected one of selection transistors, causes the selected one of the selection transistors to turn on, and causes any one of the memory transistors to turn on that is closer to the selection transistor than the selected one of the memory transistors. The control circuit also applies a second voltage lower than the first voltage to a gate of the selected one of the memory transistors. Such a potential difference between the first voltage and the second voltage causing a change in electric charges in the electric charge storage layer.

Abstract translation: 非挥发性半导体存储装置包括执行擦除操作以从存储晶体管中选定的一个擦除数据的控制电路。 控制电路向所选择的一个选择晶体管的另一端施加第一电压，使所选择的一个选择晶体管导通，并且使存储晶体管中的任何一个导通比接近选择晶体管更接近选择晶体管 选择一个存储晶体管。 控制电路还将低于第一电压的第二电压施加到所选存储晶体管的栅极。 第一电压和第二电压之间的这种电位差导致电荷存储层中的电荷变化。

公开(公告)号：US08192081B2

公开(公告)日：2012-06-05

申请号：US12437614

申请日：2009-05-08

Applicant: Tatsuya Suzuki ,  Mitsunori Oi ,  Takashi Maeda ,  Norimichi Saito ,  Toshinori Nishi ,  Go Hanzawa ,  Takeshi Morita

Inventor： Tatsuya Suzuki ,  Mitsunori Oi ,  Takashi Maeda ,  Norimichi Saito ,  Toshinori Nishi ,  Go Hanzawa ,  Takeshi Morita

IPC: G01K7/16 ,  G01K1/08 ,  G01K1/14

CPC classification number: G01K1/12 ,  G01K13/02 ,  G01K2205/04

Abstract: A temperature sensor including: a temperature sensing element (102) having a temperature sensing unit (103) and a pair of device electrode wires (104); a sheath member (106) having a sheath wire (108) connected at a junction (110) to at least one of the device electrode wires and a sheath outer pipe (107) retaining the sheath wire in an insulating material (114); an inner tube (112) which has a bottomed cylindrical shape; and a cylindrical outer tube (120) having an open end, covering the inner tube such that the open end is located at a front end side of the junction and in a region to the rear end side of or aligned with the front end of the inner tube, and being spaced from the inner tube at the front end side of the junction.

Abstract translation: 一种温度传感器，包括：温度感测元件（102），其具有温度感测单元（103）和一对器件电极线（104）; 护套构件（106），其具有在结（110）处连接到至少一个器件电极线的护套线（108）和将护套线保持在绝缘材料（114）中的护套外管（107）; 内管（112），其具有有底圆筒形状; 以及具有开口端的圆柱形外管（120），其覆盖所述内管，使得所述开口端位于所述接合部的前端侧，并且位于所述接合部的前端侧的区域中， 内管，并且在连接处的前端侧与内管间隔开。

公开(公告)号：US08189391B2

公开(公告)日：2012-05-29

申请号：US12620986

申请日：2009-11-18

Applicant: Kiyotaro Itagaki ,  Yoshihisa Iwata ,  Hiroyasu Tanaka ,  Masaru Kidoh ,  Masaru Kito ,  Ryota Katsumata ,  Hideaki Aochi ,  Akihiro Nitayama ,  Takashi Maeda ,  Tomoo Hishida

Inventor： Kiyotaro Itagaki ,  Yoshihisa Iwata ,  Hiroyasu Tanaka ,  Masaru Kidoh ,  Masaru Kito ,  Ryota Katsumata ,  Hideaki Aochi ,  Akihiro Nitayama ,  Takashi Maeda ,  Tomoo Hishida

IPC: G11C16/04

CPC classification number: G11C16/0483 ,  G11C16/08 ,  G11C16/16 ,  G11C16/26 ,  G11C16/30

Abstract: A non-volatile semiconductor storage device includes: a memory string including a plurality of memory cells connected in series; a first selection transistor having one end connected to one end of the memory string; a first wiring having one end connected to the other end of the first selection transistor; a second wiring connected to a gate of the first selection transistor. A control circuit is configured to boost voltages of the second wiring and the first wiring in the erase operation, while keeping the voltage of the first wiring greater than the voltage of the second wiring by a certain potential difference. The certain potential difference is a potential difference that causes a GIDL current.

Abstract translation: 非易失性半导体存储装置包括：包括串联连接的多个存储单元的存储串; 第一选择晶体管，其一端连接到存储器串的一端; 第一布线，其一端连接到第一选择晶体管的另一端; 连接到第一选择晶体管的栅极的第二布线。 控制电路被配置为在保持第一布线的电压大于第二布线的电压一定电位差的同时，在擦除操作中提高第二布线和第一布线的电压。 某些电位差是导致GIDL电流的电位差。

公开(公告)号：US08182145B2

公开(公告)日：2012-05-22

申请号：US12437646

申请日：2009-05-08

Applicant: Tatsuya Suzuki ,  Mitsunori Oi ,  Takashi Maeda ,  Norimichi Saito ,  Toshinori Nishi ,  Go Hanzawa ,  Takeshi Morita

Inventor： Tatsuya Suzuki ,  Mitsunori Oi ,  Takashi Maeda ,  Norimichi Saito ,  Toshinori Nishi ,  Go Hanzawa ,  Takeshi Morita

IPC: G01K1/08 ,  G01K7/16

Abstract: A temperature sensor including a temperature sensing element (102) having a temperature sensing unit (103) and a pair of device electrode wires (104) extending from the temperature sensing unit; a sheath member (106) including a sheath wire (108) connected at a junction (110) to one of the device electrode wires and a sheath outer pipe (107) retaining the sheath wire in an insulating material (114); an inner tube (112) which has a bottomed cylindrical shape, the inner tube accommodating the temperature sensing element and the junction in a bottom portion side of the inner tube serving as a leading end of the temperature sensor, and extending in an extension direction of the device electrode wire and the sheath wire; and an outer tube (120) which has a bottomed cylindrical shape including a gas inlet hole (122a, 122b, 122c), the outer tube covering the inner tube, and being spaced, from the inner tube on a leading end side of the junction when viewed in a direction perpendicular to an axial direction of the inner tube.