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81.发明申请Nonvolatile Memory Device Having Authentication, and Methods of Operation and Manufacture Thereof 有权具有认证的非易失性存储器件及其操作和制造方法公开(公告)号：US20150310203A1
公开(公告)日：2015-10-29
申请号：US14706305
申请日：2015-05-07
CPC分类号： G06F21/44 , G06F21/79 , G06K19/07745 , H01L24/48 , H01L24/49 , H01L2224/05554 , H01L2224/05644 , H01L2224/32145 , H01L2224/32245 , H01L2224/48091 , H01L2224/48145 , H01L2224/48247 , H01L2224/48464 , H01L2224/49113 , H01L2224/73265 , H01L2224/85399 , H01L2924/00014 , H01L2924/181 , H04L9/0894 , H01L2924/00012 , H01L2924/00 , H01L2924/013 , H01L2924/01014 , H01L2924/0105 , H01L2224/45015 , H01L2924/207 , H01L2224/45099
摘要： A memory device package encloses two separate die, one being a standard nonvolatile memory integrated circuit (“IC”) die, and the other being any suitable authentication IC die. Either die may be stacked upon the other, or the die may be placed side-by-side. The external contacts may correspond to the power and signal requirements of the standard nonvolatile memory IC die so that the pin-out of the memory device package may present a standard pinout. The power and signal requirements of the authentication IC die may be satisfied with some or all of the pins for the nonvolatile memory integrated circuit die, or with other unused pins of the device package. One or more additional external contacts may be added exclusively for the authentication integrated circuit die. One or more signals may be dedicated as between the standard nonvolatile memory IC die and the authentication IC die.
摘要翻译： 存储器件封装封装两个分离的管芯，一个是标准的非易失性存储器集成电路（“IC”）管芯，另一个是任何合适的认证IC管芯。 可以将模具堆叠在另一个上，或者模具可以并排放置。 外部触点可以对应于标准非易失性存储器IC芯片的功率和信号要求，使得存储器件封装的引脚输出可以呈现标准引脚。 认证IC芯片的功率和信号要求可以用于非易失性存储器集成电路管芯的一些或全部引脚，或与器件封装的其它未使用的引脚相兼容。 一个或多个附加的外部触点可以专门用于认证集成电路管芯。 一个或多个信号可以专用于标准非易失性存储器IC管芯和认证IC管芯之间。
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公开(公告)号：US20150228342A1
公开(公告)日：2015-08-13
申请号：US14697148
申请日：2015-04-27
发明人： Jongjun Kim , Eungjoon Park
IPC分类号： G11C16/06
摘要： A flash memory device may operate from two supply voltages, one being provided externally, and the other being generated within the flash memory device from the external supply voltage. The flash memory device may be provided with a selectable-level buffer for interfacing with either low supply voltage or high supply voltage integrated circuits. To provide even greater flexibility, the flash memory device may be provided with the capability of receiving a second supply voltage from an external source, which may take precedence over the internally-generated second supply voltage or may be combined with the internally-generated second supply voltage.
摘要翻译： 闪存器件可以从两个电源电压操作，一个从外部提供，另一个从外部电源电压在闪存器件内产生。 闪存器件可以设置有用于与低电源电压或高电源电压集成电路接口的可选级缓冲器。 为了提供更大的灵活性，闪存器件可以具有从外部源接收第二电源电压的能力，其可以优先于内部产生的第二电源电压，或者可以与内部产生的第二电源 电压。
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公开(公告)号：US09082499B2
公开(公告)日：2015-07-14
申请号：US14249944
申请日：2014-04-10
发明人： Oron Michael
CPC分类号： G11C16/26
摘要： A Flash memory device operable under a single-bit or multiple-bit serial protocol is provided with a capability to determine the address boundary condition of an application from the address field of an address boundary configurable (“ABC”) read command. Based on the identified address boundary condition, the Flash memory device may perform multiple sensing of the memory array as required by the ABC read command using optimal internal sense times for each sensing. The number of dummy bytes may be specified for the read command in advance by the user, based on the address boundary of the application and the desired frequency of operation of the Flash memory device. Therefore, Flash memory device read performance is improved both by minimizing the number of dummy bytes in the read command and by optimizing the internal sense times for the read operation.
摘要翻译： 在单位或多位串行协议下可操作的闪速存储器件具有从地址边界可配置（“ABC”）读取命令的地址字段确定应用的地址边界条件的能力。 基于所识别的地址边界条件，闪存器件可以使用针对每个感测的最佳内部检测时间来执行ABC读取命令所要求的存储器阵列的多次感测。 可以基于应用的地址边界和闪存设备的期望操作频率，由用户预先为读取命令指定虚拟字节的数量。 因此，通过最小化读取命令中的虚拟字节数以及通过优化读取操作的内部检测时间来提高闪存器件读取性能。
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84.发明申请Nonvolatile Memory Device Having Authentication, and Methods of Operation and Manufacture Thereof 有权具有认证的非易失性存储器件及其操作和制造方法公开(公告)号：US20140245384A1
公开(公告)日：2014-08-28
申请号：US13780803
申请日：2013-02-28
IPC分类号： G06F21/78
CPC分类号： G06F21/44 , G06F21/79 , G06K19/07745 , H01L24/48 , H01L24/49 , H01L2224/05554 , H01L2224/05644 , H01L2224/32145 , H01L2224/32245 , H01L2224/48091 , H01L2224/48145 , H01L2224/48247 , H01L2224/48464 , H01L2224/49113 , H01L2224/73265 , H01L2224/85399 , H01L2924/00014 , H01L2924/181 , H04L9/0894 , H01L2924/00012 , H01L2924/00 , H01L2924/013 , H01L2924/01014 , H01L2924/0105 , H01L2224/45015 , H01L2924/207 , H01L2224/45099
摘要： A memory device package encloses two separate die, one being a standard nonvolatile memory integrated circuit (“IC”) die, and the other being any suitable authentication IC die. Either die may be stacked upon the other, or the die may be placed side-by-side. The external contacts may correspond to the power and signal requirements of the standard nonvolatile memory IC die so that the pin-out of the memory device package may present a standard pinout. The power and signal requirements of the authentication IC die may be satisfied with some or all of the pins for the nonvolatile memory integrated circuit die, or with other unused pins of the device package. One or more additional external contacts may be added exclusively for the authentication integrated circuit die. One or more signals may be dedicated as between the standard nonvolatile memory IC die and the authentication IC die.
摘要翻译： 存储器件封装封装两个分离的管芯，一个是标准的非易失性存储器集成电路（“IC”）管芯，另一个是任何合适的认证IC管芯。 可以将模具堆叠在另一个上，或者模具可以并排放置。 外部触点可以对应于标准非易失性存储器IC芯片的功率和信号要求，使得存储器件封装的引脚输出可以呈现标准引脚。 认证IC芯片的功率和信号要求可以用于非易失性存储器集成电路管芯的一些或全部引脚，或者与器件封装的其它未使用的引脚相兼容。 一个或多个附加的外部触点可以专门用于认证集成电路管芯。 一个或多个信号可以专用于标准非易失性存储器IC管芯和认证IC管芯之间。
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公开(公告)号：US20040170035A1
公开(公告)日：2004-09-02
申请号：US10792760
申请日：2004-03-05
发明人： An-Tung Chen , Yung-Peng Hwang
IPC分类号： H02M001/00
CPC分类号： H02M3/1584
摘要： A stable voltage converter is described. The stable voltage converter has an error amplifier, a plurality of subtraction circuits, a plurality of converter channels, and a plurality of current sensors. The error amplifier compares a reference voltage and an average output voltage to generate an error signal for stabilizing the output voltage of the converter. The subtraction circuits input the error signal and channel current signals generated by the current sensors, and then output modified error signals for controlling the converter channels to adequately output direct current power outputs.
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公开(公告)号：US20040047224A1
公开(公告)日：2004-03-11
申请号：US10238048
申请日：2002-09-06
发明人： Chang Wan Ha
IPC分类号： G11C008/00
摘要： In accordance with an embodiment of the present invention, a semiconductor memory includes a memory array having a plurality of rows and columns of sectors, a horizontal global row decoder, a vertical global row decoder, and a plurality of horizontal local row decoders. Each of the sectors has a plurality of rows and columns of memory cells. The horizontal global row decoder is configured to select one of the rows of sectors in response to a first set of row address signals. The vertical global row decoder is configured to select one or two adjacent columns of the columns of sectors in response to a second set of row address signals. The plurality of horizontal local row decoders are coupled to the vertical global row decoder and the horizontal global row decoder to select one or two adjacent sectors located at the intersection of the selected row of sectors and the selected one or two adjacent columns of sectors.
摘要翻译： 根据本发明的实施例，半导体存储器包括具有多个行和列的扇区的存储器阵列，水平全局行解码器，垂直全局行解码器和多个水平局部行解码器。 每个扇区具有多个行和列的存储单元。 水平全局行解码器被配置为响应于第一组行地址信号来选择扇区行之一。 垂直全局行解码器被配置为响应于第二组行地址信号来选择扇区列的一个或两个相邻列。 多个水平局部行解码器被耦合到垂直全局行解码器和水平全局行解码器，以选择位于所选择的扇区行和所选择的一个或两个相邻列的行的相交处的一个或两个相邻扇区。
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公开(公告)号：US20040027851A1
公开(公告)日：2004-02-12
申请号：US10329259
申请日：2002-12-23
发明人： Thomas C.J. Lai
IPC分类号： G11C011/24
CPC分类号： G11C11/40615 , G11C7/18 , G11C11/405 , G11C11/406 , G11C11/4087 , G11C11/4097
摘要： The present invention discloses a memory cell and circuit with multiple bit lines, which can allow two word lines and bit lines in the same memory block to access different memory cells in the memory block. The memory cell with multiple bit lines according to the present invention comprises a capacitor, at least two transistor switches, at least two word line terminals, and at least two bit line terminals. At least two transistor switches are connected at one end to the capacitor. At least two word line terminals are used to control the connection between the two transistor switches. At least two bit line terminals are connected to the other end of the two transistor switches opposite the capacitor.
摘要翻译： 本发明公开了一种具有多个位线的存储单元和电路，其可以允许同一存储器块中的两个字线和位线访问存储块中的不同存储单元。 根据本发明的具有多个位线的存储单元包括电容器，至少两个晶体管开关，至少两个字线端子和至少两个位线端子。 至少两个晶体管开关在一端连接到电容器。 至少两个字线端子用于控制两个晶体管开关之间的连接。 至少两个位线端子连接到与电容器相对的两个晶体管开关的另一端。
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公开(公告)号：US20030173613A1
公开(公告)日：2003-09-18
申请号：US10387476
申请日：2003-03-14
发明人： Bor-Ru Sheu , Ming-Chung Chiang , Chung-Ming Chu , Min-Chieh Yang
IPC分类号： H01L027/108 , H01L029/76 , H01L029/94 , H01L031/119
CPC分类号： H01L21/7687 , H01L21/76897 , H01L27/10855 , H01L28/75 , H01L28/90
摘要： The memory-storage node of the present invention includes a semiconductor substrate, a first insulating layer over the substrate, a conductive layer formed within the first insulating layer, and a barrier layer formed over the conductive layer. The barrier layer, preferably contains a ruthenium-based material, is conductively coupled with the conductive layer. The memory-storage node further includes a first electrode over the barrier layer, a dielectric layer over the first electrode, and a second electrode over the dielectric layer. The method for fabricating the memory storage-node of the present invention provides a semiconductor substrate and forms a first insulating layer on the substrate. A first opening is formed in the first insulating layer and a conductive layer is provided in the first opening. A barrier layer is then formed in the first opening and over the conductive layer. The barrier layer, preferably contains a ruthenium-based material, is conductively coupled with the conductive layer. A second insulating layer is formed over the first insulating layer and the barrier layer. A second opening is formed in the second insulating layer to expose a portion of the underlying barrier layer. A first electrode is formed in the second opening and a dielectric layer is formed on the second insulating layer and the first electrode. Finally, a second electrode is formed over the dielectric layer.
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公开(公告)号：US20030126488A1
公开(公告)日：2003-07-03
申请号：US10252780
申请日：2002-09-23
发明人： Chie Yeon Chen , Chuang Huang Kuo
IPC分类号： G06F001/26
摘要： The present invention discloses a frequency signal enabling apparatus and the method thereof for filtering noises and glitch when entering an operating mode from a power-saving mode. When the pulse width of the input frequency signal is smaller than the threshold pulse width, it will be considered as a noise and be filtered out. When the high-level pulse width of the input frequency signal is greater than the threshold, a first short pulse will be generated. When the low-level pulse width of the input frequency signal is greater than the threshold, a second short pulse will be generated. The relative position of the first short pulse and the second short pulse will be used to reconstruct the frequency signal, and the reconstructed frequency signal may serve as the operating frequency of the microprocessor or other digital IC.
摘要翻译： 本发明公开了一种频率信号使能装置及其从省电模式进入操作模式时对噪声和毛刺进行滤波的方法。 当输入频率信号的脉冲宽度小于阈值脉冲宽度时，将被视为噪声并被滤除。 当输入频率信号的高电平脉冲宽度大于阈值时，将产生第一短脉冲。 当输入频率信号的低电平脉冲宽度大于阈值时，将产生第二短脉冲。 将使用第一短脉冲和第二短脉冲的相对位置来重建频率信号，并且重建的频率信号可以用作微处理器或其它数字IC的工作频率。
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公开(公告)号：US20030119267A1
公开(公告)日：2003-06-26
申请号：US10024545
申请日：2001-12-21
发明人： Wen-Yueh Jang
IPC分类号： H01L021/336
CPC分类号： H01L29/66825 , H01L21/28273 , H01L29/42336
摘要： The present invention discloses a structure of a horizontal surrounding gate (HSG) flash memory cell and a method for manufacturing the same. The HSG flash memory cell of the present invention is located on a trench of an isolation region, and a channel region of the HSG flash memory cell composed of a semiconductor film is encompassed by a tunneling oxide layer, a floating gate, and a control gate in sequence. The floating gate and the control gate are also formed on the trench below the channel region. Therefore, the leakage current of the channel can be improved, and the short channel effect cannot be induced by junction depth of a source/drain. Furthermore, the coupling capacitor between the control gate and the floating gate is increased easily by increasing the depth of the trench.
摘要翻译： 本发明公开了一种水平围栅（HSG）闪存单元的结构及其制造方法。 本发明的HSG闪存单元位于隔离区域的沟槽上，由半导体膜构成的HSG快闪存储单元的沟道区域被隧道氧化物层，浮动栅极和控制栅极包围 按顺序。 浮动栅极和控制栅极也形成在沟道区域下方的沟槽上。 因此，可以提高通道的漏电流，并且短沟道效应不能由源极/漏极的结深度引起。 此外，通过增加沟槽的深度，容易地增加控制栅和浮栅之间的耦合电容。
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