公开(公告)号：US20120104384A1

公开(公告)日：2012-05-03

申请号：US13193459

申请日：2011-07-28

Applicant: Young-Joo CHOI ,  Jae-Won SONG ,  Xun ZHU ,  Sang-Wan JIN ,  Woo-Geun LEE

Inventor： Young-Joo CHOI ,  Jae-Won SONG ,  Xun ZHU ,  Sang-Wan JIN ,  Woo-Geun LEE

IPC: H01L29/786 ,  H01L21/44

CPC classification number: H01L27/1225 ,  H01L29/41733 ,  H01L29/66969 ,  H01L29/7869 ,  H01L29/78696

Abstract: A thin-film transistor (TFT) includes a gate electrode, an oxide semiconductor pattern, a source electrode, a drain electrode and an etch stopper. The gate electrode is formed on a substrate. The oxide semiconductor pattern is disposed in an area overlapping with the gate electrode. The source electrode is partially disposed on the oxide semiconductor pattern. The drain electrode is spaced apart from the source electrode, faces the source electrode, and is partially disposed on the oxide semiconductor pattern. The etch stopper has first and second end portions. The first end portion is disposed between the oxide semiconductor pattern and the source electrode, and the second end portion is disposed between the oxide semiconductor pattern and the drain electrode. A sum of first and second overlapping length is between about 30% and about 99% of a total length of the etch stopper.

Abstract translation: 薄膜晶体管（TFT）包括栅电极，氧化物半导体图案，源电极，漏电极和蚀刻停止器。 栅电极形成在基板上。 氧化物半导体图案设置在与栅电极重叠的区域中。 源电极部分地设置在氧化物半导体图案上。 漏电极与源极间隔开，面对源电极，部分地设置在氧化物半导体图案上。 蚀刻停止器具有第一和第二端部。 第一端部设置在氧化物半导体图案和源电极之间，第二端部设置在氧化物半导体图案和漏电极之间。 第一和第二重叠长度之和在蚀刻停止器的总长度的约30％至约99％之间。

公开(公告)号：US20120018720A1

公开(公告)日：2012-01-26

申请号：US13177783

申请日：2011-07-07

Applicant: Jae-Woo PARK ,  Dong-Hoon LEE ,  Sung-Haeng CHO ,  Woo-Geun LEE ,  Hye-Young RYU ,  Young-Joo CHOI

Inventor： Jae-Woo PARK ,  Dong-Hoon LEE ,  Sung-Haeng CHO ,  Woo-Geun LEE ,  Hye-Young RYU ,  Young-Joo CHOI

IPC: H01L29/786 ,  H01L21/44

CPC classification number: H01L27/1288 ,  H01L27/1214 ,  H01L27/1225 ,  H01L27/124 ,  H01L29/458

Abstract: A display substrate includes a gate line extending in a first direction on a base substrate, a data line on the base substrate and extending in a second direction crossing the first direction, a gate insulating layer on the gate line, a thin-film transistor and a pixel electrode. The thin-film transistor includes a gate electrode electrically connected the gate line, an oxide semiconductor pattern, and source and drain electrodes on the oxide semiconductor pattern and spaced apart from each other. The oxide semiconductor pattern includes a first semiconductor pattern including indium oxide and a second semiconductor pattern including indium-free oxide. The pixel electrode is electrically connected the drain electrode.

Abstract translation: 显示基板包括在基底基板上沿第一方向延伸的栅极线，在基底基板上的数据线，并且沿与第一方向交叉的第二方向延伸，栅极线上的栅极绝缘层，薄膜晶体管和 像素电极。 薄膜晶体管包括栅电极，电极连接栅极线，氧化物半导体图案以及氧化物半导体图案上的源电极和漏电极并彼此间隔开。 氧化物半导体图案包括包括氧化铟的第一半导体图案和包含无铟氧化物的第二半导体图案。 像素电极与漏电极电连接。

公开(公告)号：US08077275B2

公开(公告)日：2011-12-13

申请号：US12408213

申请日：2009-03-20

Applicant: Byung-Duk Yang ,  Jang-Soo Kim ,  Woo-Geun Lee ,  Ki-Won Kim ,  Sang-Ki Kwak ,  Hyang-Shik Kong ,  Sang-Hun Lee

Inventor： Byung-Duk Yang ,  Jang-Soo Kim ,  Woo-Geun Lee ,  Ki-Won Kim ,  Sang-Ki Kwak ,  Hyang-Shik Kong ,  Sang-Hun Lee

IPC: G02F1/1339 ,  G02F1/1335

CPC classification number: G02F1/136204 ,  G02F1/13392 ,  G02F1/1341 ,  G02F2001/133388

Abstract: A display substrate includes a transistor layer, a plurality of color filters, a first blocking member, a supporting member, a circuit part, a second blocking member and a protruding member. The first blocking member is disposed between different color filters. The supporting member maintains a distance between a base substrate and a substrate facing the base substrate. A circuit part is disposed in a peripheral area surrounding a display area, and the circuit part includes a metal pattern and a contact electrode in contact with the metal pattern. The second blocking member includes substantially the same material as the first blocking member and the second blocking member covers the circuit part. The protruding member includes substantially the same material as the second blocking member, and is integrally formed with the second blocking member.

Abstract translation: 显示基板包括晶体管层，多个滤色器，第一阻挡构件，支撑构件，电路部分，第二阻挡构件和突出构件。 第一阻挡构件设置在不同的滤色器之间。 支撑构件保持基底基板和面向基底基板的基板之间的距离。 电路部分设置在围绕显示区域的周边区域中，并且电路部分包括与金属图案接触的金属图案和接触电极。 第二阻挡构件包括与第一阻挡构件基本相同的材料，并且第二阻挡构件覆盖电路部分。 突出构件包括与第二阻挡构件基本相同的材料，并且与第二阻挡构件一体地形成。

公开(公告)号：US20110297930A1

公开(公告)日：2011-12-08

申请号：US13151102

申请日：2011-06-01

Applicant: Seung-Ha CHOI ,  Kyoung-Jae Chung ,  Woo-Geun Lee

Inventor： Seung-Ha CHOI ,  Kyoung-Jae Chung ,  Woo-Geun Lee

IPC: H01L29/786 ,  H01L21/44

CPC classification number: H01L21/76804 ,  G02F1/133345 ,  G02F1/136227 ,  G02F1/136286 ,  H01L21/76816 ,  H01L27/1225 ,  H01L27/1244 ,  H01L27/1248 ,  H01L29/4908 ,  H01L29/66969 ,  H01L29/78606 ,  H01L29/7869

Abstract: A TFT display panel having a high charge mobility and making it possible to obtain uniform electric characteristics with respect to a large-area display is provided as well as a manufacturing method thereof. A TFT display panel includes a gate electrode formed on an insulation substrate, a first gate insulting layer formed of SiNx on the gate electrode, a second gate insulting layer formed of SiOx on the first gate insulting layer, an oxide semiconductor layer formed to overlap the gate electrode and having a channel part, and a passivation layer formed of SiOx on the oxide semiconductor layer and the gate electrode, and the passivation layer includes a contact hole exposing the drain electrode. The contact hole has a shape in which the passivation layer of a portion directly exposed together with a metal occupies an area smaller than the upper passivation layer.

Abstract translation: 提供具有高电荷迁移率并且可以获得相对于大面积显示器的均匀电特性的TFT显示面板及其制造方法。 TFT显示面板包括形成在绝缘基板上的栅极电极，栅极上由SiNx形成的第一栅极绝缘层，在第一栅极绝缘层上由SiOx形成的第二栅极绝缘层，形成为与栅极电极重叠的氧化物半导体层 栅电极，并具有通道部分，以及由氧化物半导体层和栅电极上的SiO x形成的钝化层，并且钝化层包括暴露漏电极的接触孔。 接触孔具有直接与金属一起暴露的部分的钝化层占据比上钝化层小的形状。

公开(公告)号：US20110284852A1

公开(公告)日：2011-11-24

申请号：US13049783

申请日：2011-03-16

Applicant: Ki-Won KIM ,  Kap-Soo Yoon ,  Woo-Geun Lee ,  Yeong-Keun Kwon ,  Hye-Young Ryu ,  Jin-Won Lee ,  Hyun-Jung Lee

Inventor： Ki-Won KIM ,  Kap-Soo Yoon ,  Woo-Geun Lee ,  Yeong-Keun Kwon ,  Hye-Young Ryu ,  Jin-Won Lee ,  Hyun-Jung Lee

IPC: H01L29/786 ,  H01L21/336

CPC classification number: H01L29/7869 ,  H01L27/1225 ,  H01L27/124 ,  H01L29/78645 ,  H01L29/78648

Abstract: A thin-film transistor includes a semiconductor pattern, a first gate electrode, a source electrode, a drain electrode and a second gate electrode. The semiconductor pattern is formed on a substrate. A first conductive layer has a pattern that includes the first gate electrode which is electrically insulated from the semiconductor pattern. A second conductive layer has a pattern that includes a source electrode electrically connected to the semiconductor pattern, a drain electrode spaced apart from the source electrode, and a second gate electrode electrically connected to the first gate electrode. The second gate electrode is electrically insulated from the semiconductor pattern, the source electrode and the drain electrode.

Abstract translation: 薄膜晶体管包括半导体图案，第一栅电极，源电极，漏电极和第二栅电极。 半导体图案形成在基板上。 第一导电层具有包括与半导体图案电绝缘的第一栅电极的图案。 第二导电层具有图案，其包括电连接到半导体图案的源电极，与源电极间隔开的漏电极和与第一栅电极电连接的第二栅电极。 第二栅电极与半导体图案，源电极和漏电极电绝缘。

公开(公告)号：US20110272696A1

公开(公告)日：2011-11-10

申请号：US13092882

申请日：2011-04-22

Applicant: Hye-Young RYU ,  Jin-Won LEE ,  Woo-Geun LEE ,  Hee-Jun BYEON ,  Xun ZHU

Inventor： Hye-Young RYU ,  Jin-Won LEE ,  Woo-Geun LEE ,  Hee-Jun BYEON ,  Xun ZHU

IPC: H01L29/786 ,  H01L33/08 ,  H01L21/44

CPC classification number: H01L27/1288 ,  H01L27/1214 ,  H01L27/1225 ,  H01L27/1248 ,  H01L27/3272 ,  H01L51/5253 ,  H01L2227/323

Abstract: A thin film transistor panel includes a substrate, a light blocking layer on the substrate, a first protective film on the light blocking layer, a first electrode and a second electrode on the first protective film, an oxide semiconductor layer on a portion of the first protective film exposed between the first electrode and the second electrode, an insulating layer, a third electrode overlapping with the oxide semiconductor layer and on the insulating layer, and a fourth electrode on the insulating layer. The light blocking layer includes first sidewalls, and the first protective film includes second sidewalls. The first and the second sidewalls are disposed along substantially the same line.

Abstract translation: 薄膜晶体管面板包括基板，基板上的阻光层，遮光层上的第一保护膜，第一保护膜上的第一电极和第二电极，第一保护膜的一部分上的氧化物半导体层 在第一电极和第二电极之间暴露的保护膜，绝缘层，与氧化物半导体层重叠的绝缘层和绝缘层上的第四电极。 遮光层包括第一侧壁，并且第一保护膜包括第二侧壁。 第一和第二侧壁沿着基本相同的线设置。

公开(公告)号：US20110175088A1

公开(公告)日：2011-07-21

申请号：US13004665

申请日：2011-01-11

Applicant: Jong In Kim ,  Young-Wook Lee ,  Jean-Ho Song ,  Jae-Hyoung Yoon ,  Sung-Ryul Kim ,  Byeong-Beom Kim ,  Je-Hyeong Park ,  Woo-Geun Lee

Inventor： Jong In Kim ,  Young-Wook Lee ,  Jean-Ho Song ,  Jae-Hyoung Yoon ,  Sung-Ryul Kim ,  Byeong-Beom Kim ,  Je-Hyeong Park ,  Woo-Geun Lee

IPC: H01L29/786 ,  H01L21/28

CPC classification number: H01L27/1225 ,  H01L27/124 ,  H01L27/1288

Abstract: A thin-film transistor (TFT) substrate having reduced defects is fabricated using a reduced number of masks. The TFT substrate includes gate wiring formed on a substrate. The gate wiring includes a gate electrode. A semiconductor pattern is formed on the gate wiring. An etch-stop pattern is formed on the semiconductor pattern. Data wiring includes a source electrode which is formed on the semiconductor pattern and the etch-stop pattern. Each of the gate wiring and the data wiring includes a copper-containing layer and a buffer layer formed on or under the copper-containing layer.

Abstract translation: 使用减少数量的掩模制造具有减少的缺陷的薄膜晶体管（TFT）基板。 TFT基板包括形成在基板上的栅极布线。 栅极布线包括栅电极。 在栅极布线上形成半导体图形。 在半导体图案上形成蚀刻停止图案。 数据布线包括形成在半导体图案上的源电极和蚀刻停止图案。 栅极布线和数据布线中的每一个包括在含铜层上形成的含铜层和缓冲层。

公开(公告)号：US20110168997A1

公开(公告)日：2011-07-14

申请号：US13006591

申请日：2011-01-14

Applicant: Young-Wook LEE ,  Woo-Geun LEE ,  Ki-Won KIM ,  Hyun-Jung LEE ,  Ji-Soo OH

Inventor： Young-Wook LEE ,  Woo-Geun LEE ,  Ki-Won KIM ,  Hyun-Jung LEE ,  Ji-Soo OH

IPC: H01L29/786 ,  H01L21/336

CPC classification number: H01L27/124 ,  H01L21/76834 ,  H01L27/1225 ,  H01L27/1255 ,  H01L27/1262 ,  H01L27/127 ,  H01L27/1288 ,  H01L29/7869 ,  H01L29/78693

Abstract: A thin film transistor (TFT) array substrate and a manufacturing method thereof are provided. The TFT array substrate may include a gate line disposed on a substrate and including a gate line and a gate electrode, an oxide semiconductor layer pattern disposed on the gate electrode, a data line disposed on the oxide semiconductor layer pattern and including a source electrode and a drain electrode of a thin film transistor (TFT) together with the gate electrode, and a data line extending in a direction intersecting the gate line, and etch stop patterns disposed at an area where the TFT is formed between the source/drain electrodes and the oxide semiconductor layer pattern and at an area where the gate line and the data line overlap each other between the gate line and the data line.

Abstract translation: 提供薄膜晶体管（TFT）阵列基板及其制造方法。 TFT阵列基板可以包括设置在基板上的栅极线，包括栅极线和栅电极，设置在栅电极上的氧化物半导体层图案，设置在氧化物半导体层图案上的数据线，并且包括源电极和 薄膜晶体管（TFT）的漏电极和栅电极以及沿着与栅极线交叉的方向延伸的数据线，以及蚀刻停止图案，设置在源极/漏极之间形成TFT的区域，以及 氧化物半导体层图案和栅极线与数据线在栅极线与数据线之间重叠的区域。

公开(公告)号：US07928440B2

公开(公告)日：2011-04-19

申请号：US12332117

申请日：2008-12-10

Applicant: Woo-Geun Lee ,  Jae-Hyoung Youn ,  Ki-Won Kim ,  Jong-In Kim

Inventor： Woo-Geun Lee ,  Jae-Hyoung Youn ,  Ki-Won Kim ,  Jong-In Kim

IPC: H01L29/04 ,  H01L29/15 ,  H01L27/12

CPC classification number: H01L27/124 ,  G02F1/136286

Abstract: A display substrate includes a base substrate, a gate line, a gate insulation layer, a data line, a thin-film transistor (TFT) and a pixel electrode. The gate line is extended in a first direction on the base substrate. The gate insulation layer is formed on the base substrate to cover the gate line. The data line is extended in a second direction and intersects the gate line at an intersecting portion. At the intersecting portion, the data line is separated from the gate line by an air gap. In another embodiment, the data line also includes at least one etching hole extending to the air gap. The TFT is electrically connected to the data and the gate lines. The pixel electrode is electrically connected to the TFT.

Abstract translation: 显示基板包括基底基板，栅极线，栅极绝缘层，数据线，薄膜晶体管（TFT）和像素电极。 栅极线在基底基板上沿第一方向延伸。 栅极绝缘层形成在基底基板上以覆盖栅极线。 数据线在第二方向上延伸并且在相交部分与栅极线相交。 在交叉部分，数据线通过气隙与栅极线分离。 在另一个实施例中，数据线还包括延伸到气隙的至少一个蚀刻孔。 TFT与数据和栅极线电连接。 像素电极电连接到TFT。

公开(公告)号：US20110079776A1

公开(公告)日：2011-04-07

申请号：US12772836

申请日：2010-05-03

Applicant: Young-Joo Choi ,  Woo-Geun Lee ,  Hye-Young Ryu ,  Ki-Won Kim

Inventor： Young-Joo Choi ,  Woo-Geun Lee ,  Hye-Young Ryu ,  Ki-Won Kim

IPC: H01L33/26

CPC classification number: H01L27/124 ,  C23F1/02 ,  C23F1/18 ,  C23F1/26 ,  H01L21/32134 ,  H01L21/465 ,  H01L27/1225

Abstract: A display device includes a gate pattern, a semiconductor pattern, a source pattern and a pixel electrode are provided. The gate pattern is formed on a base substrate and includes a gate line and a gate electrode. The semiconductor pattern is formed on the base substrate having the gate pattern and includes an oxide semiconductor. The source pattern is formed from a data metal layer and formed on the base substrate having the semiconductor pattern, and includes a data line, a source electrode and a drain electrode. The data metal layer includes a first copper alloy layer, and a lower surface of the data metal layer substantially coincides with an upper surface of the semiconductor pattern. The pixel electrode is formed on the base substrate having the source pattern and electrically connected to the drain electrode. Thus, manufacturing processes may be simplified, and reliability may be improved.

Abstract translation: 显示装置包括栅极图案，半导体图案，源图案和像素电极。 栅极图案形成在基底基板上，并且包括栅极线和栅电极。 半导体图案形成在具有栅极图案的基底基板上，并且包括氧化物半导体。 源图案由数据金属层形成并形成在具有半导体图案的基底基板上，并且包括数据线，源电极和漏电极。 数据金属层包括第一铜合金层，数据金属层的下表面基本上与半导体图案的上表面重合。 像素电极形成在具有源极图案的基底基板上并与漏电极电连接。 因此，可以简化制造工艺，并且可以提高可靠性。