公开(公告)号：US20200327088A1

公开(公告)日：2020-10-15

申请号：US16914339

申请日：2020-06-27

申请人： Swadesh Choudhary ,  Debendra Das Sharma ,  Lee Albion

发明人： Swadesh Choudhary ,  Debendra Das Sharma ,  Lee Albion

IPC分类号： G06F13/42 ,  G06F1/10

摘要： An interface for coupling an agent to a fabric supports a load/store interconnect protocol and includes a header channel implemented on a first subset of a plurality of physical lanes, the first subset of lanes including first lanes to carry a header of a packet based on the interconnect protocol and second lanes to carry metadata for the header. The interface additionally includes a data channel implemented on a separate second subset of the plurality of physical lanes, the second subset of lanes including third lanes to carry a payload of the packet and fourth lanes to carry metadata for the payload.

公开(公告)号：US10671476B2

公开(公告)日：2020-06-02

申请号：US15761405

申请日：2015-09-26

申请人： Intel Corporation ,  Daniel S. Froelich ,  Debendra Das Sharma ,  Fulvio Spagna ,  Per E. Fornberg ,  David Edward Bradley

发明人： Daniel S. Froelich ,  Debendra Das Sharma ,  Fulvio Spagna ,  Per E. Fornberg ,  David Edward Bradley

IPC分类号： G06F11/08 ,  G06F13/14 ,  G06F11/10 ,  G06F11/22 ,  H04L1/00

摘要： There is disclosed in an example an interconnect apparatus having: a root circuit; and a downstream circuit comprising at least one receiver; wherein the root circuit is operable to provide a margin test directive to the downstream circuit during a normal operating state; and the downstream circuit is operable to perform a margin test and provide a result report of the margin test to the root circuit. This may be performed in-band, for example in the L0 state. There is also disclosed a system comprising such an interconnect, and a method of performing margin testing.

公开(公告)号：US20190324523A1

公开(公告)日：2019-10-24

申请号：US16457930

申请日：2019-06-29

申请人： Michelle C. Jen ,  David J. Harriman ,  Zuoguo Wu ,  Debendra Das Sharma ,  Noam Dolev Geldbard

发明人： Michelle C. Jen ,  David J. Harriman ,  Zuoguo Wu ,  Debendra Das Sharma ,  Noam Dolev Geldbard

IPC分类号： G06F1/3234 ,  G06F1/3225 ,  G06F3/06

摘要： A device includes physical layer (PHY) circuitry including a physical coding sublayer, where the PHY circuitry is configured to alternatively support at least two different power control settings. The device further includes an interface to couple the PHY circuitry to a media access control (MAC) layer, where the interface comprises a set of data pins, a set of command pins, a set of status pins, one or more clock pins, and a plurality of power control pins to receive an indication of a particular one of the at least two power control settings. The PHY circuitry is to apply parameters corresponding to the particular control setting during operation based on the indication.

公开(公告)号：US20190042380A1

公开(公告)日：2019-02-07

申请号：US15990372

申请日：2018-05-25

申请人： Debendra Das Sharma ,  Daniel S. Froelich

发明人： Debendra Das Sharma ,  Daniel S. Froelich

IPC分类号： G06F11/22 ,  G06F13/42

摘要： A port of a computing device includes multiple receiver-transmitter pairs, each of the receiver-transmitter pairs including a respective receiver and a respective transmitter. The device further includes state machine logic that detects a training sequence received by a particular one of the receiver-transmitter pairs on a particular lane from a tester device. The training sequence includes a value to indicate a test of the particular receiver-transmitter pair by the tester device. The particular receiver-transmitter pair enters a first link state in association with the test and one or more other receiver-transmitter pairs of the port enter a second link state different from the first link state in association with the test to cause crosstalk to be generated on the particular lane during the test.

公开(公告)号：US20150186057A1

公开(公告)日：2015-07-02

申请号：US14142733

申请日：2013-12-27

申请人： Debendra Das Sharma ,  Mohan J. Kumar ,  Balin T. Fleischer

发明人： Debendra Das Sharma ,  Mohan J. Kumar ,  Balin T. Fleischer

IPC分类号： G06F3/06 ,  G06F11/20 ,  G06F13/32

CPC分类号： G06F9/52 ,  G06F3/0619 ,  G06F3/0661 ,  G06F3/0688 ,  G06F9/467 ,  G06F11/2017 ,  G06F12/0815 ,  G06F12/0817 ,  G06F12/1081 ,  G06F13/1663 ,  G06F13/32 ,  G06F13/4022 ,  G06F2212/1056 ,  G11C14/009

摘要： An apparatus for providing data coherency is described herein. The apparatus includes a global persistent memory. The global persistent memory is accessed using a protocol that includes input/output (I/O) semantics and memory semantics. The apparatus also includes a reflected memory region. The reflected memory region is a portion of the global persistent memory, and each node of a plurality of nodes maps the reflected memory region into a space that is not cacheable. Further, the apparatus includes a semaphore memory. The semaphore memory provides a hardware assist for enforced data coherency.

摘要翻译： 这里描述了一种用于提供数据一致性的装置。 该装置包括全局持久存储器。 使用包含输入/输出（I / O）语义和内存语义的协议来访问全局永久存储器。 该装置还包括反射存储区域。 反射的存储器区域是全局持久存储器的一部分，并且多个节点的每个节点将反射的存储器区域映射到不可高速缓存的空间中。 此外，该装置包括信号量存储器。 信号量存储器为强制数据一致性提供硬件辅助。

公开(公告)号：US08782318B2

公开(公告)日：2014-07-15

申请号：US13039119

申请日：2011-03-02

申请人： Debendra Das Sharma ,  Chandra P. Joshi ,  Gurushankar Rajamani

发明人： Debendra Das Sharma ,  Chandra P. Joshi ,  Gurushankar Rajamani

IPC分类号： G06F13/36 ,  G06F13/20

CPC分类号： G06F13/387

摘要： Methods and apparatus relating to increase Input Output Hubs in constrained link based multi-processor systems are described. In one embodiment, a first input output hub (IOH) and a second IOH are coupled a link interconnect and a plurality of processors, coupled to the first and second IOHs include pre-allocated resources for a single IOH. Other embodiments are also disclosed and claimed.

摘要翻译： 描述了在基于约束链路的多处理器系统中增加输入输出中枢的方法和装置。 在一个实施例中，耦合到链路互连的第一输入输出集线器（IOH）和第二IOH耦合到耦合到第一和第二IOH的多个处理器包括用于单个IOH的预先分配的资源。 还公开并要求保护其他实施例。

公开(公告)号：US20140189427A1

公开(公告)日：2014-07-03

申请号：US13892894

申请日：2013-05-13

申请人： Prahladachar Jayaprakash Bharadwaj ,  Alexander Brown ,  Debendra Das Sharma ,  Junaid Thaliyil

发明人： Prahladachar Jayaprakash Bharadwaj ,  Alexander Brown ,  Debendra Das Sharma ,  Junaid Thaliyil

IPC分类号： G06F11/14

CPC分类号： G06F11/0745 ,  G06F11/0736 ,  G06F11/0793 ,  G06F11/1415 ,  G06F11/1443

摘要： A packet is identified at a port of a serial data link, and it is determined that the packet is associated with an error. Entry into an error recovery mode is initiated based on the determination that the packet is associated with the error. Entry into the error recovery mode can cause the serial data link to be forced down. In one aspect, forcing the data link down causes all subsequent inbound packets to be dropped and all pending outbound requests and completions to be aborted during the error recovery mode.

摘要翻译： 在串行数据链路的端口处识别分组，并且确定分组与错误相关联。 基于确定该分组与该错误相关联来进入错误恢复模式。 进入错误恢复模式可能导致串行数据链路被强制关闭。 在一个方面，强制数据链路断开导致所有后续入站分组被丢弃，并且所有待处理的出站请求和完成将在错误恢复模式期间中止。

公开(公告)号：US20140112339A1

公开(公告)日：2014-04-24

申请号：US14060191

申请日：2013-10-22

申请人： Robert J. Safranek ,  Robert G. Blankenship ,  Venkatraman Iyer ,  Jeff Willey ,  Robert Beers ,  Darren S. Jue ,  Arvind A. Kumar ,  Debendra Das Sharma ,  Jeffrey C. Swanson ,  Bahaa Fahim ,  Vedaraman Geetha ,  Aaron T. Spink ,  Fulvio Spagna ,  Rahul C. Shah ,  Sitaraman V. Iyer ,  Bill Harry Nale ,  Abhishek Das ,  Simon P. Johnson ,  Yuvraj S. Dhillon ,  Yen-Cheng Liu ,  Raj K. Ramanujan ,  Robert A. Maddox ,  Herbert H. Hum ,  Ashish Gupta

发明人： Robert J. Safranek ,  Robert G. Blankenship ,  Venkatraman Iyer ,  Jeff Willey ,  Robert Beers ,  Darren S. Jue ,  Arvind A. Kumar ,  Debendra Das Sharma ,  Jeffrey C. Swanson ,  Bahaa Fahim ,  Vedaraman Geetha ,  Aaron T. Spink ,  Fulvio Spagna ,  Rahul C. Shah ,  Sitaraman V. Iyer ,  Bill Harry Nale ,  Abhishek Das ,  Simon P. Johnson ,  Yuvraj S. Dhillon ,  Yen-Cheng Liu ,  Raj K. Ramanujan ,  Robert A. Maddox ,  Herbert H. Hum ,  Ashish Gupta

IPC分类号： H04L12/741

CPC分类号： G06F13/22 ,  G06F1/3287 ,  G06F8/71 ,  G06F8/73 ,  G06F8/77 ,  G06F9/30145 ,  G06F9/44505 ,  G06F9/466 ,  G06F11/1004 ,  G06F12/0806 ,  G06F12/0808 ,  G06F12/0813 ,  G06F12/0815 ,  G06F12/0831 ,  G06F12/0833 ,  G06F13/4022 ,  G06F13/4068 ,  G06F13/4221 ,  G06F13/4282 ,  G06F13/4286 ,  G06F13/4291 ,  G06F2212/1016 ,  G06F2212/2542 ,  G06F2212/622 ,  H04L9/0662 ,  H04L12/4641 ,  H04L45/74 ,  H04L49/15 ,  Y02D10/13 ,  Y02D10/14 ,  Y02D10/151 ,  Y02D10/40 ,  Y02D10/44 ,  Y02D30/30

摘要： A physical layer (PHY) is coupled to a serial, differential link that is to include a number of lanes. The PHY includes a transmitter and a receiver to be coupled to each lane of the number of lanes. The transmitter coupled to each lane is configured to embed a clock with data to be transmitted over the lane, and the PHY periodically issues a blocking link state (BLS) request to cause an agent to enter a BLS to hold off link layer flit transmission for a duration. The PHY utilizes the serial, differential link during the duration for a PHY associated task selected from a group including an in-band reset, an entry into low power state, and an entry into partial width state

摘要翻译： 物理层（PHY）耦合到将包括多个通道的串行差分链路。 PHY包括发射机和接收机，以耦合到车道数量的每个车道。 耦合到每个通道的发射机被配置为将时钟嵌入到要在该通道上发送的数据，并且PHY周期性地发出阻塞链路状态（BLS）请求，以使代理进入BLS以阻止链路层飞行传输， 持续时间 PHY在从包括带内复位，进入低功率状态的进入和进入部分宽度状态的组中选择的PHY相关联任务的持续时间期间利用串行差分链路

公开(公告)号：US08549183B2

公开(公告)日：2013-10-01

申请号：US12883781

申请日：2010-09-16

申请人： Jasmin Ajanovic ,  Mahesh Wagh ,  Prashant Sethi ,  Debendra Das Sharma ,  David Harriman ,  Mark Rosenbluth ,  Ajay Bhatt ,  Peter Barry ,  Scott Dion Rodgers ,  Anil Vasudevan ,  Sridhar Muthrasanallur ,  James Akiyama ,  Robert Blankenship ,  Ohad Falik ,  Abraham Mendelson ,  Ilan Pardo ,  Eran Tamari ,  Eliezer Weissmann ,  Doron Shamia

发明人： Jasmin Ajanovic ,  Mahesh Wagh ,  Prashant Sethi ,  Debendra Das Sharma ,  David Harriman ,  Mark Rosenbluth ,  Ajay Bhatt ,  Peter Barry ,  Scott Dion Rodgers ,  Anil Vasudevan ,  Sridhar Muthrasanallur ,  James Akiyama ,  Robert Blankenship ,  Ohad Falik ,  Abraham Mendelson ,  Ilan Pardo ,  Eran Tamari ,  Eliezer Weissmann ,  Doron Shamia

IPC分类号： G06F3/00 ,  G06F5/00

CPC分类号： G06F12/0831 ,  G06F1/3203 ,  G06F1/324 ,  G06F1/3253 ,  G06F12/0815 ,  G06F13/385 ,  G06F13/4045 ,  G06F13/4068 ,  G06F13/4265 ,  G06F2212/621 ,  H04L12/66 ,  Y02D10/126 ,  Y02D10/151

摘要： A method and apparatus for enhancing/extending a serial point-to-point interconnect architecture, such as Peripheral Component Interconnect Express (PCIe) is herein described. Temporal and locality caching hints and prefetching hints are provided to improve system wide caching and prefetching. Message codes for atomic operations to arbitrate ownership between system devices/resources are included to allow efficient access/ownership of shared data. Loose transaction ordering provided for while maintaining corresponding transaction priority to memory locations to ensure data integrity and efficient memory access. Active power sub-states and setting thereof is included to allow for more efficient power management. And, caching of device local memory in a host address space, as well as caching of system memory in a device local memory address space is provided for to improve bandwidth and latency for memory accesses.

公开(公告)号：US08473642B2

公开(公告)日：2013-06-25

申请号：US13198559

申请日：2011-08-04

申请人： Jasmin Ajanovic ,  Mahesh Wagh ,  Prashant Sethi ,  Debendra Das Sharma ,  David Harriman ,  Mark Rosenbluth ,  Ajay Bhatt ,  Peter Barry ,  Scott Dion Rodgers ,  Anil Vasudevan ,  Sridhar Muthrasanallur ,  James Akiyama ,  Robert Blankenship ,  Ohad Falik ,  Abraham Mendelson ,  Ilan Pardo ,  Eran Tamari ,  Eliezer Weissmann ,  Doron Shamia

发明人： Jasmin Ajanovic ,  Mahesh Wagh ,  Prashant Sethi ,  Debendra Das Sharma ,  David Harriman ,  Mark Rosenbluth ,  Ajay Bhatt ,  Peter Barry ,  Scott Dion Rodgers ,  Anil Vasudevan ,  Sridhar Muthrasanallur ,  James Akiyama ,  Robert Blankenship ,  Ohad Falik ,  Abraham Mendelson ,  Ilan Pardo ,  Eran Tamari ,  Eliezer Weissmann ,  Doron Shamia

IPC分类号： G06F3/00 ,  G06F12/00

CPC分类号： G06F12/0831 ,  G06F1/3203 ,  G06F1/324 ,  G06F1/3253 ,  G06F12/0815 ,  G06F13/385 ,  G06F13/4045 ,  G06F13/4068 ,  G06F13/4265 ,  G06F2212/621 ,  H04L12/66 ,  Y02D10/126 ,  Y02D10/151

摘要： A method and apparatus for enhancing/extending a serial point-to-point interconnect architecture, such as Peripheral Component Interconnect Express (PCIe) is herein described. Temporal and locality caching hints and prefetching hints are provided to improve system wide caching and prefetching. Message codes for atomic operations to arbitrate ownership between system devices/resources are included to allow efficient access/ownership of shared data. Loose transaction ordering provided for while maintaining corresponding transaction priority to memory locations to ensure data integrity and efficient memory access. Active power sub-states and setting thereof is included to allow for more efficient power management. And, caching of device local memory in a host address space, as well as caching of system memory in a device local memory address space is provided for to improve bandwidth and latency for memory accesses.

摘要翻译： 这里描述了用于增强/扩展串行点对点互连架构的方法和装置，例如外围组件互连Express（PCIe）。 提供了时间和地点缓存提示和预取提示，以改进系统范围的缓存和预取。 包括用于仲裁系统设备/资源之间的所有权的原子操作的消息代码，以便有效地访问/拥有共享数据。 提供的松散的事务排序，同时将对应的事务优先级保持到内存位置，以确保数据完整性和高效的内存访问。 包括有功功率子状态及其设置以允许更有效的电源管理。 并且，提供设备本地存储器在主机地址空间中的缓存以及设备本地存储器地址空间中的系统存储器的缓存，以提高存储器访问的带宽和延迟。