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    Power control circuit, semiconductor device and transceiver circuit using the same
    81.
    发明授权
    Power control circuit, semiconductor device and transceiver circuit using the same 有权
    电源控制电路，半导体器件和收发电路使用相同

    公开(公告)号：US07415254B2

    公开(公告)日：2008-08-19

    申请号：US11272917

    申请日：2005-11-15

    申请人： Akira Kuriyama ,  Satoshi Tanaka

    发明人： Akira Kuriyama ,  Satoshi Tanaka

    IPC分类号： H04B1/04 ,  H01Q11/12

    CPC分类号： H03G3/3047 ,  H03G3/02 ,  H03G3/3042

    摘要： There is provided a power control circuit having a stable high-speed operation, and a semiconductor device and a transceiver circuit using it. The power control circuit controls the gain of an amplifier so that power outputted from the amplifier reaches a desired value according to a digital control signal. The power control circuit includes a digital feedback loop which converts a detected signal obtained by detecting a value of the output power of the amplifier to a digital signal, determines a differential between the digital signal and the digital control signal, converts the differential to an analog signal and outputs a first feedback signal, an analog feedback loop which outputs a high frequency element corresponding to a differential between an analog signal to which the digital control signal is converted and the detected signal, as a second feedback signal, and an adder which determines the sum of the first and the second feedback signal and outputs a gain control signal for controlling the gain of the amplifier.

    摘要翻译： 提供了具有稳定的高速操作的功率控制电路，以及使用它的半导体器件和收发器电路。 功率控制电路控制放大器的增益，使得从放大器输出的功率根据数字控制信号达到期望值。 功率控制电路包括数字反馈回路，其将通过将放大器的输出功率的值检测到的检测信号转换为数字信号，确定数字信号和数字控制信号之间的差分，将差分转换为模拟 信号并输出​​第一反馈信号，模拟反馈回路，其输出对应于转换数字控制信号的模拟信号与检测信号之间的差分的高频元件作为第二反馈信号，以及加法器，其确定 第一和第二反馈信号的和，并输出用于控制放大器的增益的增益控制信号。

    Semiconductor integrated circuit device
    82.
    发明授权
    Semiconductor integrated circuit device 失效
    半导体集成电路器件

    公开(公告)号：US07414821B2

    公开(公告)日：2008-08-19

    申请号：US11898946

    申请日：2007-09-18

    申请人： Kumiko Takikawa ,  Satoshi Tanaka ,  Masumi Kasahara

    发明人： Kumiko Takikawa ,  Satoshi Tanaka ,  Masumi Kasahara

    IPC分类号： H02H9/00

    CPC分类号： H01L27/0259 ,  H01L27/0255 ,  H03F1/52 ,  H03F2200/372

    摘要： Into an internal circuit to operate in a high-frequency band, there is incorporated a protective circuit of a multistage connection which is constructed to include a plurality of diode-connected transistors having a low parasitic capacity and free from a malfunction even when an input signal higher than the power supply voltage is applied. Into an internal circuit to operate in a low-frequency band, there is incorporated a protective circuit which is constructed to include one diode-connected transistor. The protective circuits include two lines of protective circuit, in which the directions of electric currents are so reversed as to protect the internal circuits against positive/negative static electricities.

    摘要翻译： 在内部电路中工作在高频带内，结合有多级连接的保护电路，其被构造为包括具有低寄生电容并且没有故障的多个二极管连接的晶体管，即使当输入信号 高于施加电源电压。 在内部电路中工作在低频带，其中包括一个保护电路，其构造为包括一个二极管连接的晶体管。 保护电路包括两条保护电路，其中电流方向相反，以保护内部电路免受正/负静电。

    Fabrication of semiconductor device for flash memory with increased select gate width
    85.
    发明授权
    Fabrication of semiconductor device for flash memory with increased select gate width 有权
    具有增加选择栅极宽度的闪存半导体器件制造

    公开(公告)号：US07365018B2

    公开(公告)日：2008-04-29

    申请号：US11319895

    申请日：2005-12-28

    申请人： Masaaki Higashitani ,  Tuan Pham ,  Masayuki Ichige ,  Koji Hashimoto ,  Satoshi Tanaka ,  Kikuko Sugimae

    发明人： Masaaki Higashitani ,  Tuan Pham ,  Masayuki Ichige ,  Koji Hashimoto ,  Satoshi Tanaka ,  Kikuko Sugimae

    IPC分类号： H01L21/302

    CPC分类号： H01L21/28123 ,  H01L21/32139 ,  H01L27/115 ,  H01L27/11521 ,  H01L27/11524

    摘要： A non-volatile memory device having memory elements with a channel length of, e.g., 45-55 nm or less, is fabricated using existing lithographic techniques. In one approach, patterns of first and second photomasks are transferred to the same photoresist layer. The first photomask can have openings with a given feature size F that are spaced apart by the feature size F, for instance. The second photomask has an opening which is sized to create a desired inter-select gate gap, such as 3 F or 5 F. A third photomask is used to provide protective portions in a second photoresist layer over the select gate structures. The final structure has memory elements of width F spaced apart by a distance F, and select gates of width 3 F spaced apart by 3 F or 5 F. In another approach, the patterns of three photomasks are transferred to respective photoresist layers to create an analogous final structure.

    摘要翻译： 使用现有的光刻技术制造具有例如45-55nm或更小的通道长度的存储元件的非易失性存储器件。 在一种方法中，第一和第二光掩模的图案被转移到相同的光致抗蚀剂层。 第一光掩模可以具有例如由特征尺寸F间隔开的具有给定特征尺寸F的开口。 第二光掩模具有一个开口，其尺寸被设计成产生期望的选择性间隙，例如3F或5F。第三光掩模用于在选择栅极结构上的第二光致抗蚀剂层中提供保护部分。 最终结构具有间隔开距离F的宽度为F的存储元件，并且以3F或5F隔开的宽度3F的选择栅极。另一种方法是将三个光掩模的图案转移到相应的光致抗蚀剂层，以形成 类似的最终结构。

    Receiver, receiving method and portable wireless apparatus
    86.
    发明授权
    Receiver, receiving method and portable wireless apparatus 有权
    接收机，接收方式和便携式无线设备

    公开(公告)号：US07346325B2

    公开(公告)日：2008-03-18

    申请号：US11179553

    申请日：2005-07-13

    申请人： Koji Maeda ,  Satoshi Tanaka ,  Irei Kyu ,  Yukinori Akamine ,  Manabu Kawabe

    发明人： Koji Maeda ,  Satoshi Tanaka ,  Irei Kyu ,  Yukinori Akamine ,  Manabu Kawabe

    IPC分类号： H04B1/10

    CPC分类号： H04B1/30

    摘要： This invention provides a receiver in which the calibration time by repeated operations to correct phase mismatch and amplitude mismatch between I and Q signals can be reduced. The receiver comprises mixers which convert received RF signals into quadrature modulated IF signals, signal paths which filter and amplify and output the quadrature modulated signals output from the mixers, a calibration circuit which calibrates phase and amplitude mismatches between the I and Q components of the quadrature modulated signals output through the signal paths, a frequency converter which, when the mixers or the signal paths selected output calibration signals with IF frequency instead of the quadrature modulated signals, converts the calibration signals into those with a frequency higher than IF frequency, and an arithmetic operation circuit which calculates phase and amplitude mismatches from the calibration signals output by the frequency converter and outputs calculation results. The calibration circuit executes calibration, using the calculation results.

    摘要翻译： 本发明提供一种接收机，其中通过重复操作来校正I和Q信号之间的相位失配和幅度失配的校准时间可以减少。 该接收机包括将接收的RF信号转换为正交调制的IF信号的混频器，对从混频器输出的正交调制信号进行滤波和放大并输出的信号路径;校准电路，其校准正交的I和Q分量之间的相位和幅度失配 调制信号通过信号路径输出，频率转换器，当混频器或信号路径选择输出具有IF频率而不是正交调制信号的校准信号时，将校准信号转换为频率高于IF频率的校准信号， 算术运算电路，从由变频器输出的校准信号计算相位和幅度失配，并输出计算结果。 校准电路使用计算结果执行校准。

    Phase locked loop circuit
    88.
    发明授权
    Phase locked loop circuit 有权
    锁相环电路

    公开(公告)号：US07301405B2

    公开(公告)日：2007-11-27

    申请号：US11202266

    申请日：2005-08-12

    申请人： Manabu Kawabe ,  Kazuyuki Hori ,  Satoshi Tanaka ,  Yukinori Akamine ,  Masumi Kasahara ,  Kazuo Watanabe

    发明人： Manabu Kawabe ,  Kazuyuki Hori ,  Satoshi Tanaka ,  Yukinori Akamine ,  Masumi Kasahara ,  Kazuo Watanabe

    IPC分类号： H03L7/00

    CPC分类号： H03L7/107 ,  H03C3/0925 ,  H03C3/0941 ,  H03C3/0991 ,  H03L7/1974 ,  H03L7/1976

    摘要： The present invention provides a PLL circuit containing a loop gain circuit capable of suppressing loop gain variation. This PLL circuit includes a counter that is driven by a voltage controlled oscillator within the PLL circuit, an accumulator (ACL) that accumulates the output of the counter, and a comparison operation circuit block that compares the count value of the ACL and the design value pre-stored in a register, and the loop gain of the PLL circuit is detected taking advantage of the fact that the ACL count value is inversely proportional to the loop gain. Based on the detection result, the loop gain is calibrated by correcting the loop gain with a charge pump current, etc. This allows the PLL circuit to maintain stable loop characteristics that will not affect the characteristics variation of each element constituting the PLL.

    摘要翻译： 本发明提供一种包含能够抑制环路增益变化的环路增益电路的PLL电路。 该PLL电路包括由PLL电路内的压控振荡器驱动的计数器，累加计数器的输出的累加器（ACL），以及将ACL的计数值与设计值进行比较的比较运算电路块 预先存储在寄存器中，并且利用ACL计数值与循环增益成反比的事实来检测PLL电路的环路增益。 基于检测结果，通过用电荷泵电流等校正环路增益来校准环路增益。这允许PLL电路保持不会影响构成PLL的每个元件的特性变化的稳定环路特性。

    Semiconductor integrated circuit device
    89.
    发明授权
    Semiconductor integrated circuit device 有权
    半导体集成电路器件

    公开(公告)号：US07298600B2

    公开(公告)日：2007-11-20

    申请号：US11104541

    申请日：2005-04-13

    申请人： Kumiko Takikawa ,  Satoshi Tanaka ,  Masumi Kasahara

    发明人： Kumiko Takikawa ,  Satoshi Tanaka ,  Masumi Kasahara

    IPC分类号： H01C7/12

    CPC分类号： H01L27/0259 ,  H01L27/0255 ,  H03F1/52 ,  H03F2200/372

    摘要： Into an internal circuit to operate in a high-frequency band, there is incorporated a protective circuit of a multistage connection which is constructed to include a plurality of diode-connected transistors having a low parasitic capacity and free from a malfunction even when an input signal higher than the power supply voltage is applied. Into an internal circuit to operate in a low-frequency band, there is incorporated a protective circuit which is constructed to include one diode-connected transistor. The protective circuits include two lines of protective circuit, in which the directions of electric currents are so reversed as to protect the internal circuits against positive/negative static electricities.

    摘要翻译： 在内部电路中工作在高频带内，结合有多级连接的保护电路，其被构造为包括具有低寄生电容并且没有故障的多个二极管连接的晶体管，即使当输入信号 高于施加电源电压。 在内部电路中工作在低频带，其中包括一个保护电路，其构造为包括一个二极管连接的晶体管。 保护电路包括两条保护电路，其中电流方向相反，以保护内部电路免受正/负静电。

    PLASMA PROCESSING METHOD AND PLASMA PROCESSING APPARATUS
    90.
    发明申请
    PLASMA PROCESSING METHOD AND PLASMA PROCESSING APPARATUS 有权
    等离子体处理方法和等离子体处理装置

    公开(公告)号：US20070227665A1

    公开(公告)日：2007-10-04

    申请号：US11694126

    申请日：2007-03-30

    申请人： Naoki Matsumoto ,  Chishio Koshimizu ,  Manabu Iwata ,  Satoshi Tanaka

    发明人： Naoki Matsumoto ,  Chishio Koshimizu ,  Manabu Iwata ,  Satoshi Tanaka

    IPC分类号： C23F1/00 ,  H01L21/465

    CPC分类号： H01L21/31116 ,  H01J37/32091 ,  H01J37/32174 ,  H01J37/32623 ,  H01J37/32706 ,  H01J37/32935

    摘要： A plasma processing method performs a desired plasma process on substrates by using a plasma generated in a processing space. A first and a second electrode are disposed in parallel in a processing vessel that is grounded, the substrate is supported on the second electrode to face the first electrode, the processing vessel is vacuum evacuated, a desired processing gas is supplied into the processing space formed between the first electrode, the second electrode and a sidewall of the processing vessel, and a first radio frequency power is supplied to the second electrode. The first electrode is connected to the processing vessel via an insulator or a space, and is electrically coupled to a ground potential via a capacitance varying unit whose electrostatic capacitance is varied based on a process condition of the plasma process performed on the substrate.

    摘要翻译： 等离子体处理方法通过使用在处理空间中产生的等离子体在衬底上进行所需的等离子体处理。 第一电极和第二电极平行放置在接地的处理容器中，基板被支撑在第二电极上以面对第一电极，处理容器被真空抽真空，所需的处理气体被供应到形成的处理空间 在第一电极，第二电极和处理容器的侧壁之间，并且向第二电极提供第一射频功率。 第一电极经由绝缘体或空间连接到处理容器，并且经由静电电容根据在衬底上进行的等离子体处理的工艺条件而变化的电容变化单元电耦合到接地电位。