公开(公告)号：US11289513B2

公开(公告)日：2022-03-29

申请号：US16074282

申请日：2018-01-19

Applicant: BOE TECHNOLOGY GROUP CO., LTD.

Inventor： Ke Wang ,  Hehe Hu ,  Xinhong Lu

IPC: H01L27/12

Abstract: A thin film transistor and a method for fabricating the same, an array substrate and a display device are provided. The thin film transistor includes an active layer and a protective layer being provided on and in direct contact with the active layer, the protective layer is provided corresponding to a channel region of the thin film transistor; the protective layer is made of an oxygen-enriched metallic oxide insulation material which will not introduce any new element into the active layer. In the thin film transistor and the method for fabricating the same, the array substrate and the display device provided by the present disclosure, the active layer can be protected from being damaged by the etchant for forming the source/drain, and no new element will be introduced into the active layer; thus the characteristics and the stability of the thin film transistor is improved.

公开(公告)号：US11289464B2

公开(公告)日：2022-03-29

申请号：US16632167

申请日：2019-08-06

Applicant: BOE TECHNOLOGY GROUP CO., LTD.

Inventor： Zhiwei Liang ,  Yingwei Liu ,  Muxin Di ,  Ke Wang ,  Zhanfeng Cao ,  Shibo Jiao

IPC: H01L25/16 ,  H01L27/12 ,  H01L23/00

Abstract: A display substrate, a method for fabricating the same, and a display device are provided. The display substrate includes: a substrate 100 that includes a first via filled with a first conductive section 4011; a drive thin film transistor that is placed on a first side of the substrate and includes a first terminal 2051; and a light emitting diode chip 300 that is placed on a second side of the substrate distal to the drive thin film transistor; wherein the light emitting diode chip 300 includes a first lead 301 and a second lead 302; the first lead 301 is in electrical contact with the first terminal 2051 through the first conductive section 4011; and the second lead 302 is in electrical contact with a second electrode 402 that is placed on the second side of the substrate.

公开(公告)号：US20210408052A1

公开(公告)日：2021-12-30

申请号：US16755652

申请日：2019-05-13

Applicant: BOE Technology Group Co., Ltd.

Inventor： Zhiwei Liang ,  Muxin Di ,  Ke Wang ,  Yingwei Liu ,  Xiaoyan Zhu ,  Zhanfeng Cao ,  Guangcai Yuan

IPC: H01L27/12 ,  H01L33/62

Abstract: An array substrate is provided. The array substrate includes a base substrate; a first bonding pad layer including a plurality of first bonding pads on a first side of the base substrate; a second bonding pad layer including a plurality of second bonding pads on a second side of the base substrate, wherein the second side is opposite to the first side; and a plurality of signal lines on a side of the second bonding pad layer away from the base substrate. A respective one of the plurality of second bonding pads extends through the base substrate to electrically connect to a respective one of the plurality of first bonding pads. The respective one of the plurality of first bonding pads includes a protruding portion protruding away from the first side of the base substrate along a direction from the second side to the first side.

公开(公告)号：US11133363B2

公开(公告)日：2021-09-28

申请号：US16556342

申请日：2019-08-30

Applicant: BOE Technology Group Co., Ltd.

Inventor： Ke Wang ,  Xinhong Lu ,  Hehe Hu ,  Wei Yang ,  Ce Ning

IPC: H01L27/32 ,  H01L27/12 ,  H01L29/40 ,  H01L29/417 ,  H01L29/423

Abstract: The present discloses an array substrate and a manufacturing method thereof, and a display device. The array substrate includes a first transistor and a second transistor. The first transistor includes a first active layer, a first gate, a first source and a first drain. The second transistor includes a second active layer, a second gate, a second source and a second drain. An orthographic projection of the second source on the base substrate and an orthographic projection of the second drain on the base substrate at least partially overlap. One of the second source and the second drain is in the same layer as and made from the same material as the first gate. The first source and the first drain are in the same layer as and made from the same material as the other of the second source and the second drain.

公开(公告)号：US11121068B2

公开(公告)日：2021-09-14

申请号：US16530605

申请日：2019-08-02

Applicant: BOE Technology Group Co., Ltd.

Inventor： Muxin Di ,  Zhiwei Liang ,  Yingwei Liu ,  Ke Wang ,  Zhanfeng Cao ,  Renquan Gu ,  Qi Yao ,  Jaiil Ryu

IPC: H01L23/498 ,  H01L21/48

Abstract: Embodiments of the present disclosure provide an array substrate, a display device, a method for manufacturing an array substrate, a method for manufacturing a display device, and a spliced display device. The array substrate includes: a base substrate in which a through hole is provided; a filling portion disposed in the through hole, including a recessed structure and made from a flexible material; an electrically conductive pattern disposed on the filling portion and at least partially located in the recessed structure; and a film layer disposed on a side of the electrically conductive pattern facing away from the base substrate.

公开(公告)号：US20200328266A1

公开(公告)日：2020-10-15

申请号：US16651551

申请日：2019-11-13

Applicant: BOE TECHNOLOGY GROUP CO., LTD.

Inventor： Yingwei Liu ,  Qi Yao ,  Ke Wang ,  Zhanfeng Cao ,  Zhiwei Liang ,  Muxin Di ,  Guangcai Yuan ,  Xue Jiang ,  Dongni Liu

IPC: H01L27/32 ,  H01L51/56 ,  H01L51/00

Abstract: The present disclosure relates to a method of manufacturing an array substrate. The method of manufacturing an array substrate may include forming a main via hole in a substrate, filling a first conductive material in the main via hole, and forming a pixel circuit layer on a first surface of the substrate. The pixel circuit layer may include a first via hole. An orthographic projection of the first via hole on the substrate may at least partially overlap the corresponding main via hole.

公开(公告)号：US20180337245A1

公开(公告)日：2018-11-22

申请号：US15865793

申请日：2018-01-09

Applicant: BOE TECHNOLOGY GROUP CO., LTD.

Inventor： Xinhong Lu ,  Ke Wang ,  Wei Yang

IPC: H01L29/49 ,  H01L29/423 ,  H01L29/417 ,  H01L21/02 ,  H01L21/311

CPC classification number: H01L29/4908 ,  H01L21/02178 ,  H01L21/02252 ,  H01L21/31116 ,  H01L29/41733 ,  H01L29/42384 ,  H01L29/78642

Abstract: A method for manufacturing a thin film transistor includes: forming a source electrode and a first insulation pattern, where an orthographic projection of the first insulation pattern at a substrate is within an orthographic projection of the source electrode at the substrate; forming an active layer, a second insulation pattern and a gate electrode on the substrate, an exposed portion of the source electrode not covered by the first insulation pattern and the first insulation pattern; exposing a first portion of the action layer on the first insulation pattern by removing parts of the gate electrode and the second insulation pattern; and performing a plasma treatment to the exposed first portion, thereby forming a drain electrode.

公开(公告)号：US09972643B2

公开(公告)日：2018-05-15

申请号：US14892067

申请日：2015-04-20

Applicant: BOE TECHNOLOGY GROUP CO., LTD.

Inventor： Zhijun LV ,  Ke Wang ,  Jiushi Wang ,  Fangzhen Zhang

IPC: H01L29/786 ,  H01L27/12 ,  H01L21/77

CPC classification number: H01L27/1225 ,  H01L21/77 ,  H01L27/12 ,  H01L27/124 ,  H01L27/1248 ,  H01L27/1262 ,  H01L2924/0002 ,  H01L2924/00

Abstract: An array substrate and a fabrication method thereof, and a display device are provided. The array substrate comprises: a thin film transistor (TFT 10) provided on a base substrate (01), a first passivation layer (200) provided on the thin film transistor (TFT 10), and a transparent electrode layer (300) provided on a surface of the first passivation layer (200). The first passivation layer (300) includes: a first sub-thin film layer (210), and a second sub-thin film layer (211) which is provided on a surface of the first sub-thin film layer (210) and in contact with the transparent electrode layer (300); and a film density of the second sub-thin film layer (211) is greater than that of the first sub-thin film layer (210).

公开(公告)号：US09741751B2

公开(公告)日：2017-08-22

申请号：US14778257

申请日：2015-04-16

Applicant: Boe Technology Group Co., Ltd.

Inventor： Ke Wang ,  Seongyeol Yoo

IPC: H01L27/12 ,  G02F1/1343 ,  G02F1/1362 ,  H01L29/786 ,  G02F1/1368

CPC classification number: H01L27/1288 ,  G02F1/13439 ,  G02F1/136286 ,  G02F1/1368 ,  G02F2001/136295 ,  H01L27/1225 ,  H01L27/124 ,  H01L27/127 ,  H01L29/66969 ,  H01L29/7869

Abstract: The present invention provides an array substrate fabricating method. The array substrate fabricating method comprises the steps of: forming a semiconductor material layer and a first photoresist layer on a substrate successively, forming a pattern of an active layer comprising thin film transistors by using the semiconductor material layer and the first photoresist layer through photoetching technology, and reserving the first photoresist layer at least on conductive areas of the active layer when the thin film transistors are turned on; and forming a first material layer on the substrate on which the active layer is formed and the first photoresist layer is reserved on the active layer, and forming a pattern comprising first structures by using the first material layer through the photoetching technology. The method is adapted for fabricating an array substrate using metal oxide thin film transistors.

公开(公告)号：US09362414B2

公开(公告)日：2016-06-07

申请号：US14416227

申请日：2014-04-16

Applicant: BOE TECHNOLOGY GROUP CO., LTD.

Inventor： Ke Wang ,  Seongyeol Yoo ,  Ce Ning ,  Wei Yang

IPC: H01L29/786 ,  H01L21/4763 ,  H01L29/51 ,  H01L29/49 ,  H01L29/66 ,  H01L29/423 ,  H01L29/417

Abstract: Provided are oxide thin-film transistor and display device employing the same, and method for manufacturing an oxide thin-film transistor array substrate. A source electrode and a drain electrode are located below an oxide active layer pattern, and a gate electrode is located below the source electrode and the drain electrode, and the gate insulating layer is located between the gate electrode and the source electrode/the drain electrode.