公开(公告)号：US07531404B2

公开(公告)日：2009-05-12

申请号：US11216596

申请日：2005-08-30

申请人： Sangwoo Pae ,  Jose Maiz ,  Justin Brask ,  Gilbert Dewey ,  Jack Kavalieros ,  Robert Chau ,  Suman Datta

发明人： Sangwoo Pae ,  Jose Maiz ,  Justin Brask ,  Gilbert Dewey ,  Jack Kavalieros ,  Robert Chau ,  Suman Datta

IPC分类号： H01L21/8238 ,  H01L21/336 ,  H01L21/8234 ,  H01L21/3205

CPC分类号： H01L21/28185 ,  H01L21/28088 ,  H01L29/495 ,  H01L29/517 ,  H01L29/66545 ,  H01L29/66553 ,  H01L29/66583

摘要： A method of forming a transistor gate stack having an annealed gate dielectric layer begins by providing a substrate that includes a first and second spacer separated by a trench. A conformal high-k gate dielectric layer is deposited on the substrate and within the trench with a thickness that ranges from 3 Å to 60 Å. Next, a capping layer is deposited on the high-k gate dielectric layer that substantially fills the trench and covers the high-k gate dielectric layer. The high-k gate dielectric layer is then annealed at a temperature that is greater than or equal to 600° C. The capping layer is removed to expose an annealed high-k gate dielectric layer. A metal layer is then deposited on the annealed high-k gate dielectric layer. A CMP process may be used to remove excess material and complete formation of the transistor gate stack.

摘要翻译： 形成具有退火栅极电介质层的晶体管栅极堆叠的方法开始于提供包括由沟槽分隔开的第一和第二间隔物的衬底。 保形高k栅极电介质层沉积在衬底上并且在沟槽内沉积，厚度范围为3埃至60埃。 接下来，在高k栅极电介质层上沉积盖层，其基本上填充沟槽并覆盖高k栅极电介质层。 然后将高k栅极电介质层在大于或等于600℃的温度下退火。去除覆盖层以暴露退火的高k栅极电介质层。 然后在退火的高k栅极电介质层上沉积金属层。 可以使用CMP工艺来去除多余的材料并完成晶体管栅叠层的形成。

公开(公告)号：US20070128820A1

公开(公告)日：2007-06-07

申请号：US11294730

申请日：2005-12-05

申请人： Amlan Majumdar ,  Suman Datta ,  Justin Brask ,  Robert Chau ,  Jack Kavalieros

发明人： Amlan Majumdar ,  Suman Datta ,  Justin Brask ,  Robert Chau ,  Jack Kavalieros

IPC分类号： H01L21/331

CPC分类号： H01L21/2652 ,  H01L29/1083 ,  H01L29/4966 ,  H01L29/517 ,  H01L29/665 ,  H01L29/66537 ,  H01L29/66545 ,  H01L29/6659

摘要： A method including introducing an implant of a dopant species into an active region of a device substrate, the dopant species comprising a conductivity type such that a conductivity of the implant is the same as a conductivity of a well of the active region wherein the introduction is aligned to junction regions of a device structure. An apparatus and system comprising an active device region of a substrate, the active device region comprising a well of a first conductivity, junction regions of a different second conductivity formed in the active region and separated by a channel and an implant of a dopant species in the well, the dopant species comprising a conductivity type such that a conductivity of the implant is the same as the first conductivity of the well and the implant is aligned to the junction regions.

摘要翻译： 一种方法，包括将掺杂剂物质的注入引入到器件衬底的有源区中，所述掺杂物种类包括导电类型，使得所述注入的导电性与所述有源区的阱的导电性相同，其中所述引入是 对准到器件结构的结区域。 一种包括衬底的有源器件区域的器件和系统，所述有源器件区域包括阱的第一导电性，形成在有源区中并由沟道形成的不同第二导电的结区域和掺杂物种类的注入 阱，包括导电类型的掺杂物种类，使得植入物的导电性与阱的第一导电性相同，并且注入物与连接区域对准。

公开(公告)号：US20060186484A1

公开(公告)日：2006-08-24

申请号：US11064996

申请日：2005-02-23

申请人： Robert Chau ,  Suman Datta ,  Jack Kavalieros ,  Justin Brask ,  Mark Doczy ,  Matthew Metz

发明人： Robert Chau ,  Suman Datta ,  Jack Kavalieros ,  Justin Brask ,  Mark Doczy ,  Matthew Metz

IPC分类号： H01L29/78 ,  H01L21/336

CPC分类号： H01L29/7848 ,  H01L29/0649 ,  H01L29/0847 ,  H01L29/1033 ,  H01L29/16 ,  H01L29/20 ,  H01L29/201 ,  H01L29/207 ,  H01L29/267 ,  H01L29/41783 ,  H01L29/4236 ,  H01L29/452 ,  H01L29/517 ,  H01L29/66522 ,  H01L29/66628 ,  H01L29/66636 ,  H01L29/66795 ,  H01L29/78 ,  H01L29/7827 ,  H01L29/7836 ,  H01L29/785 ,  H01L29/78603 ,  H01L29/78618 ,  H01L29/78681

摘要： A transistor having a narrow bandgap semiconductor source/drain region is described. The transistor includes a gate electrode formed on a gate dielectric layer formed on a silicon layer. A pair of source/drain regions are formed on opposite sides of the gate electrode wherein said pair of source/drain regions comprise a narrow bandgap semiconductor film formed in the silicon layer on opposite sides of the gate electrode.

公开(公告)号：US20060180878A1

公开(公告)日：2006-08-17

申请号：US11393151

申请日：2006-03-29

申请人： Justin Brask ,  Jack Kavalieros ,  Mark Doczy ,  Uday Shah ,  Chris Barns ,  Matthew Metz ,  Suman Datta ,  Annalisa Cappellani ,  Robert Chau

发明人： Justin Brask ,  Jack Kavalieros ,  Mark Doczy ,  Uday Shah ,  Chris Barns ,  Matthew Metz ,  Suman Datta ,  Annalisa Cappellani ,  Robert Chau

IPC分类号： H01L29/94 ,  H01L29/76 ,  H01L31/062 ,  H01L31/113 ,  H01L31/119

CPC分类号： H01L21/82345 ,  H01L21/28229 ,  H01L21/823842 ,  H01L29/513 ,  H01L29/517 ,  H01L29/66545

摘要： A method for making a semiconductor device is described. That method comprises forming a first dielectric layer on a substrate, then forming a trench within the first dielectric layer. After forming a second dielectric layer on the substrate, a first metal layer is formed within the trench on a first part of the second dielectric layer. A second metal layer is then formed on the first metal layer and on a second part of the second dielectric layer.

公开(公告)号：US20060160371A1

公开(公告)日：2006-07-20

申请号：US11037644

申请日：2005-01-18

申请人： Matthew Metz ,  Suman Datta ,  Jack Kavalieros ,  Mark Doczy ,  Justin Brask ,  Robert Chau

发明人： Matthew Metz ,  Suman Datta ,  Jack Kavalieros ,  Mark Doczy ,  Justin Brask ,  Robert Chau

IPC分类号： H01L21/31

CPC分类号： H01L21/28194 ,  H01L21/02192 ,  H01L21/022 ,  H01L21/02304 ,  H01L21/28079 ,  H01L21/3141 ,  H01L21/31691 ,  H01L29/513 ,  H01L29/517 ,  H01L29/7833

摘要： Oxidation between a higher dielectric constant material such as a rare earth oxide and a substrate may be reduced by providing a seal layer over the gate dielectric. In some embodiments, the seal layer may be isolated from the gate dielectric by a buffer layer.

摘要翻译： 通过在栅极电介质上设置密封层，可以减少较高介电常数材料如稀土氧化物与基底之间的氧化。 在一些实施例中，密封层可以通过缓冲层与栅极电介质隔离。

公开(公告)号：US20060065939A1

公开(公告)日：2006-03-30

申请号：US10951073

申请日：2004-09-27

申请人： Mark Doczy ,  Justin Brask ,  Jack Kavalieros ,  Chris Barns ,  Matthew Metz ,  Suman Datta ,  Robert Chau

发明人： Mark Doczy ,  Justin Brask ,  Jack Kavalieros ,  Chris Barns ,  Matthew Metz ,  Suman Datta ,  Robert Chau

IPC分类号： H01L29/94 ,  H01L21/3205

CPC分类号： H01L21/823437 ,  H01L21/823828

摘要： A complementary metal oxide semiconductor integrated circuit may be formed with NMOS and PMOS transistors that have high dielectric constant gate dielectric material over a semiconductor substrate. A metal barrier layer may be formed over the gate dielectric. A workfunction setting metal layer is formed over the metal barrier layer and a cap metal layer is formed over the workfunction setting metal layer.

摘要翻译： 互补金属氧化物半导体集成电路可以形成有在半导体衬底上具有高介电常数栅极电介质材料的NMOS和PMOS晶体管。 可以在栅极电介质上方形成金属阻挡层。 在金属阻挡层上方形成功函设定金属层，在功函设定金属层上形成帽金属层。

公开(公告)号：US20060063318A1

公开(公告)日：2006-03-23

申请号：US10938778

申请日：2004-09-10

申请人： Suman Datta ,  Jack Kavalieros ,  Mark Doczy ,  Matthew Metz ,  Marko Radosavljevic ,  Amlan Majumdar ,  Justin Brask ,  Robert Chau

发明人： Suman Datta ,  Jack Kavalieros ,  Mark Doczy ,  Matthew Metz ,  Marko Radosavljevic ,  Amlan Majumdar ,  Justin Brask ,  Robert Chau

IPC分类号： H01L21/336 ,  H01L21/8234

CPC分类号： H01L51/102 ,  B82Y10/00 ,  H01L51/0048 ,  H01L51/0052 ,  H01L51/0545 ,  H01L51/105

摘要： Ambipolar conduction can be reduced in carbon nanotube transistors by forming a gate electrode of a metal. Metal sidewall spacers having different workfunctions than the gate electrode may be formed to bracket the metal gate electrode.

摘要翻译： 通过形成金属的栅电极，可以在碳纳米管晶体管中减少双极传导。 可以形成具有与栅电极不同的功函数的金属侧壁间隔物以支撑金属栅电极。

公开(公告)号：US20060022271A1

公开(公告)日：2006-02-02

申请号：US10900585

申请日：2004-07-28

申请人： Matthew Metz ,  Suman Datta ,  Jack Kavalieros ,  Mark Doczy ,  Justin Brask ,  Robert Chau

发明人： Matthew Metz ,  Suman Datta ,  Jack Kavalieros ,  Mark Doczy ,  Justin Brask ,  Robert Chau

IPC分类号： H01L27/01

CPC分类号： H01L21/823462 ,  H01L21/823857

摘要： Complementary metal oxide semiconductor integrated circuits may be formed with NMOS and PMOS transistors having different gate dielectrics. The different gate dielectrics may be formed, for example, by a subtractive process. The gate dielectrics may differ in material, thickness, or formation techniques, as a few examples.

公开(公告)号：US20060006522A1

公开(公告)日：2006-01-12

申请号：US10889535

申请日：2004-07-12

申请人： Mark Doczy ,  Mitchell Taylor ,  Justin Brask ,  Jack Kavalieros ,  Suman Datta ,  Matthew Metz ,  Robert Chau ,  Jack Hwang

发明人： Mark Doczy ,  Mitchell Taylor ,  Justin Brask ,  Jack Kavalieros ,  Suman Datta ,  Matthew Metz ,  Robert Chau ,  Jack Hwang

IPC分类号： H01L23/14

CPC分类号： H01L21/823842

摘要： Complementary metal oxide semiconductor metal gate transistors may be formed by depositing a metal layer in trenches formerly inhabited by patterned gate structures. The patterned gate structures may have been formed of polysilicon in one embodiment. The metal layer may have a workfunction most suitable for forming one type of transistor, but is used to form both the n and p-type transistors. The workfunction of the metal layer may be converted, for example, by ion implantation to make it more suitable for use in forming transistors of the opposite type.

公开(公告)号：US20050287746A1

公开(公告)日：2005-12-29

申请号：US10877232

申请日：2004-06-24

申请人： Matthew Metz ,  Suman Datta ,  Jack Kavalieros ,  Mark Doczy ,  Justin Brask ,  Robert Chau

发明人： Matthew Metz ,  Suman Datta ,  Jack Kavalieros ,  Mark Doczy ,  Justin Brask ,  Robert Chau

IPC分类号： H01L21/336 ,  H01L21/8238 ,  H01L29/49 ,  H01L29/51

CPC分类号： H01L29/517 ,  H01L21/823842 ,  H01L29/495 ,  H01L29/4966 ,  H01L29/66545 ,  H01L29/66553 ,  H01L29/66772

摘要： In a metal gate replacement process, a gate electrode stack may be formed of a germanium containing layer. In subsequent processing of the source/drains, high temperature steps may be utilized, forming a germinide on said stacks. That germinide may be removed, prior to removing the rest of the stack, using H2O2.

摘要翻译： 在金属栅极替换工艺中，栅电极堆叠可以由含锗层形成。 在源/下水道的后续处理中，可以利用高温步骤，在所述堆上形成发芽。 在使用H 2 O 2 O 2除去堆叠的其余部分之前，可以除去该发芽物。