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165 条记录 (耗时 0.028 秒)

    Bottom-gate SONOS-type cell having a silicide gate
    81.
    发明申请
    Bottom-gate SONOS-type cell having a silicide gate 有权
    具有硅化物栅极的底栅SONOS型电池

    公开(公告)号：US20060205124A1

    公开(公告)日：2006-09-14

    申请号：US11077901

    申请日：2005-03-11

    申请人： S. Brad Herner

    发明人： S. Brad Herner

    IPC分类号： H01L21/84 ,  H01L21/00

    CPC分类号： H01L27/11568 ,  H01L21/84 ,  H01L27/0688 ,  H01L27/115 ,  H01L27/11578 ,  H01L27/1203 ,  Y10S438/954

    摘要： A bottom-gate thin film transistor having a silicide gate is described. This transistor is advantageously formed as SONOS-type nonvolatile memory cell, and methods are described to efficiently and robustly form a monolithic three dimensional memory array of such cells. The fabrication methods described avoid photolithography over topography and difficult stack etches of prior art monolithic three dimensional memory arrays of charge storage devices. The use of a silicide gate rather than a polysilicon gate allows increased capacitance across the gate oxide.

    摘要翻译： 描述了具有硅化物栅极的底栅薄膜晶体管。 该晶体管有利地形成为SONOS型非易失性存储单元，并且描述了有效且鲁棒地形成这种单元的单片三维存储器阵列的方法。 所描述的制造方法避免了对现有技术的电荷存储装置的单片三维存储阵列的地形和难以堆叠蚀刻的光刻。 使用硅化物栅极而不是多晶硅栅极允许跨越栅极氧化物的电容增加。

    Method for making high density nonvolatile memory
    82.
    发明授权
    Method for making high density nonvolatile memory 有权
    制造高密度非易失性存储器的方法

    公开(公告)号：US06984561B2

    公开(公告)日：2006-01-10

    申请号：US10855804

    申请日：2004-05-26

    申请人： S. Brad Herner ,  Maitreyee Mahajani

    发明人： S. Brad Herner ,  Maitreyee Mahajani

    IPC分类号： H01L21/336

    CPC分类号： G11C5/02 ,  H01L21/8238 ,  H01L23/48 ,  H01L27/1021 ,  H01L27/148 ,  H01L29/94 ,  H01L2924/0002 ,  H01L2924/00

    摘要： An improved method for fabricating a three dimensional monolithic memory with increased density. The method includes forming conductors preferably comprising tungsten, then filling and planarizing; above the conductors forming semiconductor elements preferably comprising two diode portions and an antifuse, then filling and planarizing; and continuing to form conductors and semiconductor elements in multiple stories of memories. The arrangement of processing steps and the choice of materials decreases aspect ratio of each memory cell, improving the reliability of gap fill and preventing etch undercut.

    摘要翻译： 一种用于制造密度增加的三维单片存储器的改进方法。 该方法包括形成优选包含钨的导体，然后填充和平坦化; 在形成半导体元件的导体之上，优选地包括两个二极管部分和反熔丝，然后填充和平坦化; 并在多层故事中继续形成导体和半导体元件。 处理步骤的布置和材料的选择降低了每个存储单元的纵横比，提高了间隙填充的可靠性并防止蚀刻底切。

    Selective oxidation of silicon in diode, TFT, and monolithic three dimensional memory arrays
    83.
    发明授权
    Selective oxidation of silicon in diode, TFT, and monolithic three dimensional memory arrays 有权
    二极管，TFT和单片三维存储阵列中硅的选择性氧化

    公开(公告)号：US06951780B1

    公开(公告)日：2005-10-04

    申请号：US10742204

    申请日：2003-12-18

    申请人： S. Brad Herner

    发明人： S. Brad Herner

    IPC分类号： H01L21/82 ,  H01L21/8239 ,  H01L21/84 ,  H01L27/105 ,  H01L27/115 ,  H01L27/12

    CPC分类号： H01L27/1021 ,  H01L21/84 ,  H01L27/105 ,  H01L27/1052 ,  H01L27/115 ,  H01L27/11521 ,  H01L27/11568 ,  H01L27/12

    摘要： The present invention relates to use of selective oxidation to oxidize silicon in the presence of tungsten and/or tungsten nitride in memory cells and memory arrays. This technique is especially useful in monolithic three dimensional memory arrays. In one aspect of the invention, the silicon of a diode-antifuse memory cell is selectively oxidized to repair etch damage and reduce leakage, while exposed tungsten of adjacent conductors and tungsten nitride of a barrier layer are not oxidized. In some embodiments, selective oxidation may be useful for gap fill. In another aspect of the invention, TFT arrays made up of charge storage memory cells comprising a polysilicon/tungsten nitride/tungsten gate can be subjected to selective oxidation to passivate the gate polysilicon and reduce leakage.

    摘要翻译： 本发明涉及选择性氧化在存在于存储器单元和存储器阵列中的钨和/或氮化钨存在下氧化硅的用途。 这种技术在单片三维存储器阵列中特别有用。 在本发明的一个方面，二极管 - 反熔断存储器单元的硅被选择性地氧化以修复蚀刻损伤并减少泄漏，而相邻导体的暴露的钨和阻挡层的氮化钨不被氧化。 在一些实施方案中，选择性氧化可用于间隙填充。 在本发明的另一方面，由包含多晶硅/氮化钨/钨栅极的电荷存储单元组成的TFT阵列可以进行选择性氧化以钝化栅多晶硅并减少泄漏。

    Creation and translation of low-relief texture for a photovoltaic cell
    84.
    发明授权
    Creation and translation of low-relief texture for a photovoltaic cell 失效
    光伏电池的低浮雕纹理的创建和翻译

    公开(公告)号：US08563352B2

    公开(公告)日：2013-10-22

    申请号：US12750635

    申请日：2010-03-30

    申请人： Mohamed M. Hiliali ,  S. Brad Herner

    发明人： Mohamed M. Hiliali ,  S. Brad Herner

    IPC分类号： H01L31/0236

    CPC分类号： H01L31/0236 ,  Y02E10/50

    摘要： Low-relief texture can be created by applying and firing frit paste on a silicon surface. Where frit contacts the surface at high temperature, it etches silicon, dissolving silicon in the softened glass frit. The result is a series of small, randomly located pits, which produce a near-Lambertian surface, suitable for use in a photovoltaic cell. This texturing method consumes little silicon, and is advantageously used in a photovoltaic cell in which a thin silicon lamina comprises the base region of the cell. When the lamina is formed by implanting ions in a donor wafer to form a cleave plane and cleaving the lamina from the donor wafer at the cleave plane, the ion implantation step will serve to translate texture formed at a first surface to the cleave plane, and thus to the second, opposing surface following cleaving. Low-relief texture formed by other methods can be translated from the first surface to the second surface in this way as well.

    摘要翻译： 可以通过在硅表面上施加和焙烧玻璃料膏来产生低浮雕纹理。 当玻璃料在高温下接触表面时，会腐蚀硅，将硅溶解在软化玻璃料中。 结果是一系列小的，随机位置的凹坑，其产生近Lambertian表面，适用于光伏电池。 这种纹理化方法消耗很少的硅，并且有利地用于其中薄硅层包括电池的基极区域的光伏电池中。 当通过在施主晶片中注入离子以形成解理平面并在分裂面处从施主晶片切割层而形成层板时，离子注入步骤将用于将形成在第一表面处的纹理平移至解理面，以及 从而在切割之后到达第二相对表面。 通过其他方法形成的低浮雕纹理也可以以这种方式从第一表面转换到第二表面。

    Nonvolatile memory cell operating by increasing order in polycrystalline semiconductor material
    85.
    发明授权
    Nonvolatile memory cell operating by increasing order in polycrystalline semiconductor material 有权
    非易失性存储单元通过增加多晶半导体材料的顺序来操作

    公开(公告)号：US08482973B2

    公开(公告)日：2013-07-09

    申请号：US13568834

    申请日：2012-08-07

    申请人： S. Brad Herner ,  Abhijit Bandyopadhyay

    发明人： S. Brad Herner ,  Abhijit Bandyopadhyay

    IPC分类号： G11C11/36 ,  G11C11/34 ,  G11C11/00

    CPC分类号： G11C11/36 ,  G11C5/02 ,  G11C11/39 ,  G11C17/06 ,  G11C17/16 ,  H01L27/1021

    摘要： A memory cell is provided that includes a first conductor, a second conductor, and a semiconductor junction diode between the first and second conductors. The semiconductor junction diode is not in contact with a material having a lattice mismatch of less than 12 percent with the semiconductor junction diode. In addition, no resistance-switching element having its resistance changed by application of a programming voltage by more than a factor of two is disposed between the semiconductor junction diode and the first conductor or between the semiconductor junction diode and the second conductor. Numerous other aspects are provided.

    摘要翻译： 提供了一种存储单元，其包括在第一和第二导体之间的第一导体，第二导​​体和半导体结二极管。 半导体结二极管与半导体结二极管不与具有小于12％的晶格失配的材料接触。 此外，在半导体结二极管和第一导体之间或半导体结二极管和第二导体之间设置不具有通过施加编程电压大于2的电阻而改变其电阻的电阻切换元件。 提供了许多其他方面。

    Heterojunction device comprising a semiconductor and a resistivity-switching oxide or nitride
    87.
    发明授权
    Heterojunction device comprising a semiconductor and a resistivity-switching oxide or nitride 有权
    异质结装置包括半导体和电阻率切换氧化物或氮化物

    公开(公告)号：US08227787B2

    公开(公告)日：2012-07-24

    申请号：US13007812

    申请日：2011-01-17

    申请人： Tanmay Kumar ,  S. Brad Herner

    发明人： Tanmay Kumar ,  S. Brad Herner

    IPC分类号： H01L29/02 ,  H01L47/00

    CPC分类号： H01L29/868 ,  H01L21/84 ,  H01L27/1021 ,  H01L27/2409 ,  H01L29/165 ,  H01L29/22 ,  H01L29/267 ,  H01L29/417 ,  H01L29/737 ,  H01L29/8615 ,  H01L45/04 ,  H01L45/1233 ,  H01L45/146

    摘要： In the present invention, a metal oxide or nitride compound which is a wide-band-gap semiconductor abuts a silicon, germanium, or alloy of silicon and/or germanium of the opposite conductivity type to form a p-n heterojunction. This p-n heterojunction can be used to advantage in various devices. In preferred embodiments, one terminal of a vertically oriented p-i-n heterojunction diode is a metal oxide or nitride layer, while the rest of the diode is formed of a silicon or silicon-germanium resistor. For example, a diode may include a heavily doped n-type silicon region, an intrinsic silicon region, and a nickel oxide layer serving as the p-type terminal. Many of these metal oxides and nitrides exhibit resistivity-switching behavior, and such a heterojunction diode can be used in a nonvolatile memory cell, for example in a monolithic three dimensional memory array.

    摘要翻译： 在本发明中，作为宽带隙半导体的金属氧化物或氮化物化合物与相反导电型的硅和/或锗的硅，锗或合金相接触以形成p-n异质结。 该p-n异质结可以用于各种装置中。 在优选实施例中，垂直取向的p-i-n异质结二极管的一个端子是金属氧化物或氮化物层，而二极管的其余部分由硅或硅 - 锗电阻器形成。 例如，二极管可以包括重掺杂的n型硅区，本征硅区和用作p型端的氧化镍层。 这些金属氧化物和氮化物中的许多表现出电阻率切换行为，并且这种异质结二极管可以用在非易失性存储单元中，例如在单片三维存储器阵列中。

    Method to texture a lamina surface within a photovoltaic cell
    88.
    发明授权
    Method to texture a lamina surface within a photovoltaic cell 有权
    纹理光伏电池内薄片表面的方法

    公开(公告)号：US08178419B2

    公开(公告)日：2012-05-15

    申请号：US12343420

    申请日：2008-12-23

    申请人： S. Brad Herner

    发明人： S. Brad Herner

    IPC分类号： H01L21/30

    CPC分类号： H01L31/0236 ,  H01L31/02363 ,  H01L31/028 ,  H01L31/03921 ,  H01L31/1804 ,  H01L31/1892 ,  Y02E10/547 ,  Y02E10/548 ,  Y02P70/521

    摘要： It is advantageous to create texture at the surface of a photovoltaic cell to reduce reflection and increase travel length of light within the cell. A method is disclosed to create texture at the surface of a silicon body by reacting a silicide-forming metal at the surface, where the silicide-silicon interface is non-planar, then stripping the silicide, leaving behind a textured surface. Depending on the metal and the conditions of silicide formation, the resulting surface may be faceted. The peak-to-valley height of this texturing will generally be between about 300 and about 5000 angstroms, which is well-suited for use in photovoltaic cells comprising a thin silicon lamina.

    摘要翻译： 有利的是在光伏电池的表面处产生纹理以减少反射并增加电池内的光的行进长度。 公开了一种通过使表面处的硅化物形成金属（其中硅化物 - 硅界面是非平面的）反应然后剥离硅化物，留下纹理表面来在硅体的表面上产生纹理的方法。 取决于金属和硅化物形成的条件，所得到的表面可以是刻面的。 该纹理的峰谷高度通常在约300至约5000埃之间，这非常适用于包含薄硅层的光伏电池。