公开(公告)号：US07447725B2

公开(公告)日：2008-11-04

申请号：US10982110

申请日：2004-11-05

申请人： Sang Hoo Dhong ,  Harm Peter Hofstee ,  Christian Jacobi ,  Silvia Melitta Mueller ,  Hwa-Joon Oh

发明人： Sang Hoo Dhong ,  Harm Peter Hofstee ,  Christian Jacobi ,  Silvia Melitta Mueller ,  Hwa-Joon Oh

IPC分类号： G06F7/38

CPC分类号： G06F7/49947 ,  G06F7/483 ,  G06F7/49968 ,  G06F7/49973 ,  G06F7/49989 ,  G06F2207/3828

摘要： An apparatus for controlling rounding modes in a single instruction multiple data (SIMD) floating-point unit is disclosed. The SIMD floating-point unit includes a floating-point status-and-control register (FPSCR) having a first rounding mode bit field and a second rounding mode bit field. The SIMD floating-point unit also includes means for generating a first slice and a second slice. During a floating-point operation, the SIMD floating-point unit concurrently performs a first rounding operation on the first slice and a second rounding operation on the second slice according to a bit in the first rounding mode bit field and a bit in the second rounding mode bit field within the FPSCR, respectively.

摘要翻译： 公开了一种用于在单指令多数据（SIMD）浮点单元中控制舍入模式的装置。 SIMD浮点单元包括具有第一舍入模式位字段和第二舍入模式位字段的浮点状态和控制寄存器（FPSCR）。 SIMD浮点单元还包括用于生成第一切片和第二切片的装置。 在浮点运算期间，SIMD浮点单元根据第一舍入模式位字段中的位并且在第二舍入中的位同时对第一切片进行第一舍入运算，并对第二切片进行第二舍入运算 FPSCR中的模式位字段。

公开(公告)号：US20080250414A1

公开(公告)日：2008-10-09

申请号：US12116628

申请日：2008-05-07

申请人： Daniel Alan Brokenshire ,  Harm Peter Hofstee ,  Barry L. Minor ,  Mark Richard Nutter

发明人： Daniel Alan Brokenshire ,  Harm Peter Hofstee ,  Barry L. Minor ,  Mark Richard Nutter

IPC分类号： G06F9/44 ,  G06F9/46

CPC分类号： G06F9/4862 ,  G06F15/16 ,  H04L29/06027 ,  H04L63/168 ,  H04L67/10 ,  H04L67/34

摘要： A program is into at least two object files: one object file for each of the supported processor environments. During compilation, code characteristics, such as data locality, computational intensity, and data parallelism, are analyzed and recorded in the object file. During run time, the code characteristics are combined with runtime considerations, such as the current load on the processors and the size of the data being processed, to arrive at an overall value. The overall value is then used to determine which of the processors will be assigned the task. The values are assigned based on the characteristics of the various processors. For example, if one processor is better at handling intensive computations against large streams of data, programs that are highly computationally intensive and process large quantities of data are weighted in favor of that processor. The corresponding object is then loaded and executed on the assigned processor.

摘要翻译： 一个程序进入至少两个对象文件：一个对象文件，用于每个受支持的处理器环境。 在编译过程中，将数据位置，计算强度和数据并行等代码特征分析并记录在目标文件中。 在运行时间期间，代码特征与运行时考虑相结合，例如处理器上的当前负载和正在处理的数据的大小，以达到总体值。 然后，总体值用于确定哪些处理器将被分配任务。 这些值基于各种处理器的特性分配。 例如，如果一个处理器更好地处理针对大量数据流的密集计算，则高度计算密集的程序和处理大量数据的程序对该处理器进行加权。 然后在分配的处理器上加载和执行相应的对象。

公开(公告)号：US20080222394A1

公开(公告)日：2008-09-11

申请号：US12124396

申请日：2008-05-21

申请人： Claude Basso ,  Jean Louis Calvignac ,  Chih-jen Chang ,  Gordon Taylor David ,  Harm Peter Hofstee ,  Fabrice Jean Verplanken ,  Colin Beaton Verrilli

发明人： Claude Basso ,  Jean Louis Calvignac ,  Chih-jen Chang ,  Gordon Taylor David ,  Harm Peter Hofstee ,  Fabrice Jean Verplanken ,  Colin Beaton Verrilli

IPC分类号： G06F9/30

CPC分类号： G06F9/3851 ,  G06F9/3802 ,  G06F9/4843

摘要： Systems and methods for distributing thread instructions in the pipeline of a multi-threading digital processor are disclosed. More particularly, hardware and software are disclosed for successively selecting threads in an ordered sequence for execution in the processor pipeline. If a thread to be selected cannot execute, then a complementary thread is selected for execution.

摘要翻译： 公开了在多线程数字处理器的流水线中分发线程指令的系统和方法。 更具体地，公开了硬件和软件，用于以有序序列连续选择线程以在处理器管线中执行。 如果要选择的线程无法执行，则选择补充线程执行。

公开(公告)号：US20080189670A1

公开(公告)日：2008-08-07

申请号：US12060768

申请日：2008-04-01

申请人： Sang Hoo Dhong ,  Harm Peter Hofstee ,  Stephen Douglas Posluszny ,  Joel Abraham Silberman ,  Osamu Takahashi ,  Dieter F. Wendel

发明人： Sang Hoo Dhong ,  Harm Peter Hofstee ,  Stephen Douglas Posluszny ,  Joel Abraham Silberman ,  Osamu Takahashi ,  Dieter F. Wendel

IPC分类号： G06F17/50

CPC分类号： G06F17/505

摘要： The circuit library available for logic synthesis is limited to a single dynamic circuit block or logic synthesis block. The circuit design method includes first defining the logic synthesis block and then performing logic synthesis for a predetermined logical operation to be implemented. The logic synthesis step constrained to the single logic synthesis block produces an intermediate circuit design which necessarily comprises a series of dynamic circuit blocks, each associated with a single reset signal. Once the intermediate circuit is produced, the circuit design method includes eliminating unnecessary devices from the intermediate circuit to produce a final logic circuit, and then sizing the devices in the final circuit to complete the design.

摘要翻译： 可用于逻辑合成的电路库限于单个动态电路块或逻辑合成块。 电路设计方法包括首先定义逻辑合成块，然后执行用于要实现的预定逻辑运算的逻辑合成。 限制到单个逻辑合成块的逻辑合成步骤产生中间电路设计，其必然包括一系列动态电路块，每个动态电路块与单个复位信号相关联。 一旦生成了中间电路，电路设计方法包括从中间电路中消除不必要的设备，产生最终的逻辑电路，然后对最终电路中的器件进行尺寸调整以完成设计。

公开(公告)号：US07406589B2

公开(公告)日：2008-07-29

申请号：US11127848

申请日：2005-05-12

申请人： Sang Hoo Dhong ,  Gordon Clyde Fossum ,  Harm Peter Hofstee ,  Brad William Michael ,  Silvia Melitta Mueller ,  Hwa-Joon Oh

发明人： Sang Hoo Dhong ,  Gordon Clyde Fossum ,  Harm Peter Hofstee ,  Brad William Michael ,  Silvia Melitta Mueller ,  Hwa-Joon Oh

IPC分类号： G06F7/552 ,  G06F7/544 ,  G06F7/38

CPC分类号： G06F7/483 ,  G06F7/535 ,  G06F7/5443 ,  G06F7/5525 ,  G06F9/30014 ,  G06F2207/5356

摘要： High-precision floating-point function estimates are split in two instructions each: a low precision table lookup instruction and a linear interpolation instruction. Estimates of different functions can be implemented using this scheme: A separate table-lookup instruction is provided for each different function, while only a single interpolation instruction is needed, since the single interpolation instruction can perform the interpolation step for any of the functions to be estimated. Thus, significantly less overhead is incurred than would be incurred with specialized hardware, while still maintaining a uniform FPU latency, which allows for much simpler control logic.

摘要翻译： 高精度浮点函数估计分为两个指令：低精度表查找指令和线性插值指令。 可以使用该方案来实现不同功能的估计：为每个不同的功能提供单独的表查找指令，而仅需要单个插补指令，因为单个内插指令可以执行任何功能的内插步骤 估计。 因此，与专用硬件相比，产生的开销大大降低，同时仍保持统一的FPU延迟，这允许更简单的控制逻辑。

公开(公告)号：US20080162877A1

公开(公告)日：2008-07-03

申请号：US12049324

申请日：2008-03-15

申请人： Erik Richter Altman ,  Peter George Capek ,  Michael Karl Gschwind ,  Charles Ray Johns ,  Harm Peter Hofstee ,  Martin E. Hopkins ,  James Allan Kahle ,  Sumedh W. Sathaye ,  John-David Wellman ,  Ravi Nair

发明人： Erik Richter Altman ,  Peter George Capek ,  Michael Karl Gschwind ,  Charles Ray Johns ,  Harm Peter Hofstee ,  Martin E. Hopkins ,  James Allan Kahle ,  Sumedh W. Sathaye ,  John-David Wellman ,  Ravi Nair

IPC分类号： G06F15/76 ,  G06F9/30

CPC分类号： H04L63/168 ,  H04L67/10

摘要： A computer architecture and programming model for high speed processing over broadband networks are provided. The architecture employs a consistent modular structure, a common computing module and uniform software cells. The common computing module includes a control processor, a plurality of processing units, a plurality of local memories from which the processing units process programs, a direct memory access controller and a shared main memory. A synchronized system and method for the coordinated reading and writing of data to and from the shared main memory by the processing units also are provided. A hardware sandbox structure is provided for security against the corruption of data among the programs being processed by the processing units. The uniform software cells contain both data and applications and are structured for processing by any of the processors of the network. Each software cell is uniquely identified on the network.

摘要翻译： 提供了一种用于宽带网络高速处理的计算机体系结构和编程模型。 该架构采用一致的模块化结构，通用的计算模块和统一的软件单元。 公共计算模块包括控制处理器，多个处理单元，处理单元处理程序的多个本地存储器，直接存储器存取控制器和共享主存储器。 还提供了一种用于由处理单元协调地读取和从共享主存储器写入数据的同步系统和方法。 提供了一种硬件沙盒结构，用于防止由处理单元处理的程序中的数据损坏的安全性。 统一软件单元包含数据和应用程序，并且被构造为由网络的任何处理器进行处理。 每个软件单元在网络上唯一标识。

公开(公告)号：US07363609B2

公开(公告)日：2008-04-22

申请号：US09915437

申请日：2001-07-26

申请人： Sang Hoo Dhong ,  Harm Peter Hofstee ,  Stephen Douglas Posluszny ,  Joel Abraham Silberman ,  Osamu Takahashi ,  Dieter F. Wendel

发明人： Sang Hoo Dhong ,  Harm Peter Hofstee ,  Stephen Douglas Posluszny ,  Joel Abraham Silberman ,  Osamu Takahashi ,  Dieter F. Wendel

IPC分类号： G06F17/50

CPC分类号： G06F17/505

摘要： The circuit library available for logic synthesis is limited to a single dynamic circuit block or logic synthesis block. The circuit design method includes first defining the logic synthesis block (16) and then performing logic synthesis (17) for a predetermined logical operation to be implemented. The logic synthesis step constrained to the single logic synthesis block produces an intermediate circuit design (29) which necessarily comprises a series of dynamic circuit blocks, each associated with a single reset signal. Once the intermediate circuit (29) is produced, the circuit design method includes eliminating unnecessary devices (46) from the intermediate circuit (29) to produce a final logic circuit, and then sizing the devices (48) in the final circuit to complete the design.

摘要翻译： 可用于逻辑合成的电路库限于单个动态电路块或逻辑合成块。 电路设计方法包括首先定义逻辑合成块（16），然后执行用于要实现的预定逻辑运算的逻辑合成（17）。 限制到单个逻辑合成块的逻辑合成步骤产生中间电路设计（29），其必须包括一系列与单个复位信号相关联的动态电路块。 一旦产生中间电路（29），电路设计方法包括从中间电路（29）消除不必要的装置（46）以产生最终的逻辑电路，然后对最终电路中的装置（48）进行尺寸调整以完成 设计。

公开(公告)号：US07174410B2

公开(公告)日：2007-02-06

申请号：US10418593

申请日：2003-04-17

申请人： Bernard Charles Drerup ,  Harm Peter Hofstee ,  Wendel Glenn Voigt ,  Barry Joe Wolford

发明人： Bernard Charles Drerup ,  Harm Peter Hofstee ,  Wendel Glenn Voigt ,  Barry Joe Wolford

IPC分类号： G06F13/40 ,  G06F13/42 ,  G06F13/20 ,  G06F13/14

CPC分类号： G06F13/4027

摘要： A first device is operable to communicate on an bus according to a first protocol. A bridge is also operable to communicate on the bus according to the first protocol. A second device is coupled to the bus via the bridge and operable to communicate according to a second protocol. The bridge has a memory for holding data received from the second device and is operable to translate from the second to the first protocol. The second device sends write data responsive to receiving a ready signal from the bridge, and includes memory for holding the write data that the second device has sent, but for which completion has not been signaled. The second device re-sends the write data from the memory responsive to receiving a non-completion signal via the bridge, and releases the memory for the data responsive to receiving a completion signal via the bridge.

摘要翻译： 第一设备可操作以根据第一协议在总线上进行通信。 桥接器还可操作以根据第一协议在总线上进行通信。 第二设备经由桥耦合到总线并且可操作以根据第二协议进行通信。 桥具有用于保存从第二设备接收的数据的存储器，并且可操作以从第二协议转换为第一协议。 第二设备响应于从桥接收准备信号而发送写数据，并且包括用于保存第二设备已经发送的写入数据的存储器，但是还没有发出完成信号。 响应于经由桥接器接收到非完成信号，第二设备从存储器重新发送写入数据，并且响应于经由桥接器接收完成信号而释放用于数据的存储器。

公开(公告)号：US07120748B2

公开(公告)日：2006-10-10

申请号：US10655367

申请日：2003-09-04

申请人： Michael Norman Day ,  Harm Peter Hofstee ,  Charles Roy Johns ,  James Allan Kahle ,  David Shippy ,  Thuong Quang Truong ,  Takeshi Yamazaki

发明人： Michael Norman Day ,  Harm Peter Hofstee ,  Charles Roy Johns ,  James Allan Kahle ,  David Shippy ,  Thuong Quang Truong ,  Takeshi Yamazaki

IPC分类号： G06F12/00

CPC分类号： G06F12/126

摘要： The present invention provides a system for managing cache replacement eligibility. A first address register is configured to request an address from an L1 cache. An L1 cache is configured to determine whether a requested address is in the L1 cache and, in response to a determination that a requested address is not in the L1 cache, is further configured to transmit the requested address to a range register coupled to the L1 cache. The range register is configured to generate a class identifier in response to a received requested address and to transmit the requested address and class identifier to a replacement management table coupled to the range register. The replacement management table is configured to generate L2 tag replacement control indicia in response to a received requested address and class identifier. An L2 address register is coupled to the first address register and configured to request an address from an L2 cache. An L2 cache is coupled to the L2 address register and the replacement management table and is configured to determine whether a requested address is in the L2 cache and is further configured to assign replacement eligibility of at least one set of cache lines in the L2 cache in response to received L2 tag replacement control indicia. In response to a determination that a requested address is not in the L2 cache, the L2 cache is further configured to overwrite a cache line within a set of the L2 cache as a function of the replacement eligibility.

摘要翻译： 本发明提供了一种用于管理高速缓存替换资格的系统。 第一地址寄存器被配置为从L1高速缓存请求地址。 L1缓存被配置为确定所请求的地址是否在L1高速缓存中，并且响应于所请求的地址不在L1高速缓存中的确定，还被配置为将所请求的地址发送到耦合到L1的范围寄存器 缓存。 范围寄存器被配置为响应于接收到的请求的地址生成类标识符，并将所请求的地址和类标识符发送到耦合到范围寄存器的替换管理表。 替换管理表被配置为响应于接收到的请求的地址和类标识符来生成L2标签替换控制标记。 L2地址寄存器耦合到第一地址寄存器并且被配置为从L2高速缓存请求地址。 L2缓存耦合到L2地址寄存器和替换管理表，并且被配置为确定所请求的地址是否在L2高速缓存中，并被进一步配置为在L2高速缓存中分配至少一组高速缓存行的替换资格 响应接收的L2标签替换控制标记。 响应于所请求的地址不在L2高速缓存中的确定，L2高速缓存进一步被配置为根据替换资格来覆盖L2高速缓存中的高速缓存行。

公开(公告)号：US06907477B2

公开(公告)日：2005-06-14

申请号：US10782044

申请日：2004-02-19

申请人： Erik R. Altman ,  Peter G. Capek ,  Michael Gschwind ,  Harm Peter Hofstee ,  James Allan Kahle ,  Ravi Nair ,  Sumedh Wasudeo Sathaye ,  John-David Wellman

发明人： Erik R. Altman ,  Peter G. Capek ,  Michael Gschwind ,  Harm Peter Hofstee ,  James Allan Kahle ,  Ravi Nair ,  Sumedh Wasudeo Sathaye ,  John-David Wellman

IPC分类号： G06F12/10 ,  G06F13/28 ,  G06F9/28 ,  G06F13/368

CPC分类号： G06F12/1027 ,  G06F2212/682

摘要： A method and system for attached processing units accessing a shared memory in an SMT system. In one embodiment, a system comprises a shared memory. The system further comprises a plurality of processing elements coupled to the shared memory. Each of the plurality of processing elements comprises a processing unit, a direct memory access controller and a plurality of attached processing units. Each direct memory access controller comprises an address translation mechanism thereby enabling each associated attached processing unit to access the shared memory in a restricted manner without an address translation mechanism. Each attached processing unit is configured to issue a request to an associated direct memory access controller to access the shared memory specifying a range of addresses to be accessed as virtual addresses. The associated direct memory access controller is configured to translate the range of virtual addresses into an associated range of physical addresses.

摘要翻译： 一种用于附接处理单元访问SMT系统中的共享存储器的方法和系统。 在一个实施例中，系统包括共享存储器。 该系统还包括耦合到共享存储器的多个处理元件。 多个处理单元中的每一个包括处理单元，直接存储器存取控制器和多个附加的处理单元。 每个直接存储器访问控制器包括地址转换机制，从而使得每个相关联的附属处理单元能够以无限制的方式访问共享存储器，而无需地址转换机制。 每个附加的处理单元被配置为向相关联的直接存储器访问控制器发出请求以访问指定要作为虚拟地址访问的地址范围的共享存储器。 相关联的直接存储器访问控制器被配置为将虚拟地址的范围转换为相关的物理地址范围。