公开(公告)号：US07834432B2

公开(公告)日：2010-11-16

申请号：US12480105

申请日：2009-06-08

申请人： Wu-Chang Tu ,  Geng-Shin Shen

发明人： Wu-Chang Tu ,  Geng-Shin Shen

IPC分类号： H01L23/495

CPC分类号： H01L23/3107 ,  H01L23/4951 ,  H01L23/49541 ,  H01L23/49551 ,  H01L24/45 ,  H01L24/48 ,  H01L2224/32245 ,  H01L2224/45124 ,  H01L2224/45144 ,  H01L2224/48091 ,  H01L2224/48247 ,  H01L2224/4826 ,  H01L2224/73215 ,  H01L2924/00014 ,  H01L2924/01079 ,  H01L2924/00 ,  H01L2224/45015 ,  H01L2924/207

摘要： A chip package having asymmetric molding includes a lead frame, a chip, an adhesive layer, bonding wires and a molding compound. The lead frame includes a turbulent plate and a frame body having inner lead portions and outer lead portions. The turbulent plate is bended downwards to form a concave portion. The first end of the turbulent plate is connected to the frame body, and the second end is lower than the inner lead portions. The chip is fixed under the inner lead portions through the adhesive layer. The bonding wires are connected between the chip and the inner lead portions. The molding compound encapsulates the chip, the bonding wires, and the turbulent plate. The ratio between the thickness of the molding compound over and under the concave portion is larger than 1. The thickness of the molding compound under and over the outer lead portions is not equal.

摘要翻译： 具有不对称模制的芯片封装包括引线框架，芯片，粘合剂层，接合线和模塑料。 引线框架包括湍流板和具有内引线部分和外引线部分的框体。 湍流板向下弯曲以形成凹部。 湍流板的第一端连接到框体，第二端低于内引线部。 芯片通过粘合剂层固定在内引线部分的下方。 接合线连接在芯片和内引线部分之间。 模塑料封装芯片，接合线和湍流板。 凹形部分上方和下方的模塑料的厚度之比大于1.外引线部分之下和之上的模塑料的厚度不相等。

公开(公告)号：US07700412B2

公开(公告)日：2010-04-20

申请号：US12325303

申请日：2008-12-01

申请人： Geng-Shin Shen ,  Yu-Ren Chen

发明人： Geng-Shin Shen ,  Yu-Ren Chen

IPC分类号： H01L21/44 ,  H01L21/48 ,  H01L21/50

CPC分类号： H01L23/49541 ,  H01L21/565 ,  H01L21/568 ,  H01L24/19 ,  H01L24/97 ,  H01L2224/04105 ,  H01L2224/20 ,  H01L2224/32245 ,  H01L2224/73267 ,  H01L2224/92244 ,  H01L2224/94 ,  H01L2224/97 ,  H01L2924/01033 ,  H01L2924/01082 ,  H01L2924/01094 ,  H01L2924/181 ,  H01L2224/82 ,  H01L2924/00 ,  H01L2224/03

摘要： A chip package structure includes a chip-placed frame that having an adhesive layer thereon; a chip includes a plurality of pads on an active surface thereon, and is provided on the adhesive layer; a package structure is covered around the four sides of the chip-placed frame, and the height of the package structure is larger than the height of the chips; a plurality of patterned metal traces is electrically connected to the plurality of pads, another end is extended out to cover the surface of the package structure; a patterned protective layer is covered on the patterned metal traces and another end of the patterned metal traces is exposed; a plurality of patterned UBM layer is formed on the extended surface of the patterned metal traces; and a plurality of conductive elements is formed on the patterned UBM layer and is electrically connected to one end of the exposed portion of the patterned metal traces.

摘要翻译： 芯片封装结构包括其上具有粘合剂层的芯片放置的框架; 芯片包括在其上的活性表面上的多个焊盘，并且设置在粘合剂层上; 封装结构被覆盖在芯片放置的框架的四边周围，并且封装结构的高度大于芯片的高度; 多个图案化的金属迹线电连接到多个焊盘，另一端延伸以覆盖封装结构的表面; 图案化的保护层被覆盖在图案化的金属迹线上，并且图案化的金属迹线的另一端被暴露; 在图案化的金属迹线的延伸表面上形成多个图案化的UBM层; 并且多个导电元件形成在图案化的UBM层上并且电连接到图案化金属迹线的暴露部分的一端。

公开(公告)号：US07662667B2

公开(公告)日：2010-02-16

申请号：US12325334

申请日：2008-12-01

申请人： Geng-Shin Shen

发明人： Geng-Shin Shen

IPC分类号： H01L21/44 ,  H01L21/48 ,  H01L21/50 ,  H01L21/4763

CPC分类号： H01L23/5389 ,  H01L21/568 ,  H01L21/6835 ,  H01L23/3128 ,  H01L24/19 ,  H01L24/20 ,  H01L24/25 ,  H01L24/97 ,  H01L2221/68345 ,  H01L2221/68359 ,  H01L2224/04105 ,  H01L2224/12105 ,  H01L2224/20 ,  H01L2224/211 ,  H01L2224/24137 ,  H01L2224/97 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01015 ,  H01L2924/01033 ,  H01L2924/01075 ,  H01L2924/01082 ,  H01L2924/01094 ,  H01L2924/09701 ,  H01L2924/12041 ,  H01L2924/15311 ,  H01L2224/82

摘要： A die rearrangement package structure is provided, which includes a die that having an active surface and a bottom surface, and a plurality of pads is disposed on the active surface; a package body is provided to cover a die and the active surface being exposed; a polymer material with at least one slit is provided to cover the active surface and the pads is exposed from said slits; one ends of a plurality of metal traces is electrically connected to each pads; a protective layer is provided to cover the active surface of the dies and each metal traces, and the other ends of the metal traces being exposed; a plurality of connecting elements is electrically connected other ends of the metal traces, the characterized in that: the package body is a B-stage material.

摘要翻译： 提供了一种管芯重排封装结构，其包括具有活性表面和底表面的管芯，并且多个焊盘设置在有源表面上; 提供封装体以覆盖裸片并且所述有源表面被暴露; 提供具有至少一个狭缝的聚合物材料以覆盖有源表面，并且所述焊盘从所述狭缝暴露; 多个金属迹线的一端电连接到每个焊盘; 提供保护层以覆盖管芯的活性表面和每个金属迹线，并且金属迹线的另一端被暴露; 多个连接元件与金属迹线的另一端电连接，其特征在于：封装体是B级材料。

公开(公告)号：US20090068794A1

公开(公告)日：2009-03-12

申请号：US12270679

申请日：2008-11-13

申请人： Geng-Shin Shen ,  Chun-Ying Lin

发明人： Geng-Shin Shen ,  Chun-Ying Lin

IPC分类号： H01L21/50

CPC分类号： H01L21/4857 ,  H01L21/561 ,  H01L23/3128 ,  H01L23/49558 ,  H01L24/27 ,  H01L24/29 ,  H01L24/45 ,  H01L24/48 ,  H01L24/83 ,  H01L24/85 ,  H01L24/97 ,  H01L2224/274 ,  H01L2224/2919 ,  H01L2224/45144 ,  H01L2224/48091 ,  H01L2224/48247 ,  H01L2224/73265 ,  H01L2224/83191 ,  H01L2224/83856 ,  H01L2224/85 ,  H01L2224/97 ,  H01L2924/01005 ,  H01L2924/01027 ,  H01L2924/01028 ,  H01L2924/01033 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/0665 ,  H01L2924/07802 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2924/00014 ,  H01L2924/00 ,  H01L2924/00012

摘要： A manufacturing process for a Quad Flat Non-leaded (QFN) chip package structure is provided. First, a conductive layer having recesses and a patterned solder resist layer on the conductive layer are provided, wherein the patterned solder resist layer covers the recesses of the conductive layer. A part of the conductive layer uncovered by the patterned solder resist layer is removed so as to form a patterned conductive layer. Chips are bonded onto the patterned conductive layer such that the patterned solder resist layer and the chips are at the same side of the patterned conductive layer. The chips are electrically connected to the patterned conductive layer by bonding wires, wherein the chips and the bonding wires are at the same side of the patterned conductive layer. At least one molding compound is formed and the molding compound and the patterned conductive layer are separated.

摘要翻译： 提供了一种用于四边形扁平无铅（QFN）芯片封装结构的制造工艺。 首先，提供具有凹陷的导电层和导电层上的图案化阻焊层，其中图案化阻焊层覆盖导电层的凹部。 去除由图案化的阻焊层未覆盖的导电层的一部分，以便形成图案化的导电层。 芯片被结合到图案化的导电层上，使得图案化的阻焊层和芯片在图案化导电层的同一侧。 芯片通过接合线电连接到图案化导电层，其中芯片和接合线位于图案化导电层的相同侧。 形成至少一种模塑料，并分离模塑料和图案化的导电层。

公开(公告)号：US20090068792A1

公开(公告)日：2009-03-12

申请号：US12270602

申请日：2008-11-13

申请人： Geng-Shin Shen ,  Chun-Ying Lin

发明人： Geng-Shin Shen ,  Chun-Ying Lin

IPC分类号： H01L21/50

CPC分类号： H01L21/4857 ,  H01L21/561 ,  H01L23/3128 ,  H01L23/4951 ,  H01L24/27 ,  H01L24/29 ,  H01L24/45 ,  H01L24/48 ,  H01L24/83 ,  H01L24/85 ,  H01L24/97 ,  H01L2224/274 ,  H01L2224/2919 ,  H01L2224/32225 ,  H01L2224/45144 ,  H01L2224/48091 ,  H01L2224/4824 ,  H01L2224/48247 ,  H01L2224/73215 ,  H01L2224/83191 ,  H01L2224/83856 ,  H01L2224/85 ,  H01L2224/97 ,  H01L2924/01005 ,  H01L2924/01027 ,  H01L2924/01028 ,  H01L2924/01033 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/0665 ,  H01L2924/07802 ,  H01L2924/14 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2924/18165 ,  H01L2924/00014 ,  H01L2224/83 ,  H01L2924/00 ,  H01L2924/00012

摘要： A manufacturing process for a chip package structure is provided. First, a patterned conductive layer having a plurality of first openings and a patterned solder resist layer on the patterned conductive layer are provided. A plurality of chips are bonded onto the patterned conductive layer such that the chips and the patterned solder resist layer are disposed at two opposite surfaces of the patterned conductive layer. The chips are electrically connected to the patterned conductive layer by a plurality of bonding wires passing through the first openings of the patterned conductive layer. At least one molding compound is formed to encapsulate the patterned conductive layer, the patterned solder resist layer, the chips and the bonding wires. Then, the molding compound, the patterned conductive layer and the patterned solder resist layer are separated.

摘要翻译： 提供了一种用于芯片封装结构的制造工艺。 首先，提供在图案化导电层上具有多个第一开口和图案化阻焊层的图案化导电层。 多个芯片被结合到图案化的导电层上，使得芯片和图案化的阻焊层设置在图案化的导电层的两个相对的表面处。 芯片通过穿过图案化导电层的第一开口的多个接合线电连接到图案化的导电层。 形成至少一种模塑料以封装图案化的导电层，图案化的阻焊层，芯片和接合线。 然后，分离模塑料，图案化导电层和图案化阻焊层。

公开(公告)号：US20090068789A1

公开(公告)日：2009-03-12

申请号：US12270574

申请日：2008-11-13

申请人： Geng-Shin Shen ,  Chun-Ying Lin

发明人： Geng-Shin Shen ,  Chun-Ying Lin

IPC分类号： H01L21/00

CPC分类号： H01L21/4857 ,  H01L21/561 ,  H01L23/3128 ,  H01L24/27 ,  H01L24/29 ,  H01L24/45 ,  H01L24/48 ,  H01L24/73 ,  H01L24/83 ,  H01L24/85 ,  H01L24/97 ,  H01L2224/274 ,  H01L2224/2919 ,  H01L2224/32225 ,  H01L2224/32245 ,  H01L2224/45144 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/48247 ,  H01L2224/73265 ,  H01L2224/83191 ,  H01L2224/83856 ,  H01L2224/85 ,  H01L2224/97 ,  H01L2924/01005 ,  H01L2924/01027 ,  H01L2924/01028 ,  H01L2924/01033 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/0665 ,  H01L2924/07802 ,  H01L2924/14 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2924/00014 ,  H01L2224/83 ,  H01L2924/00 ,  H01L2924/00012

摘要： A manufacturing process for a chip package structure is provided. First, a patterned conductive layer and a patterned solder resist layer on the patterned conductive layer are provided. A plurality of chips are bonded onto the patterned conductive layer such that the chips and the patterned solder resist layer are disposed at two opposite surfaces of the patterned conductive layer. The chips are electrically connected to the patterned conductive layer by a plurality of bonding wires, wherein the chips and the bonding wires are at the same side of the patterned conductive layer. A molding compound is formed to encapsulate the patterned conductive layer, the chips and the bonding wires. Then, the molding compound, the patterned conductive layer and the patterned solder resist layer are separated.

摘要翻译： 提供了一种用于芯片封装结构的制造工艺。 首先，提供图案化导电层和图案化导电层上的图案化阻焊层。 多个芯片被结合到图案化的导电层上，使得芯片和图案化的阻焊层设置在图案化的导电层的两个相对的表面处。 芯片通过多根接合线与图案化导电层电连接，其中芯片和接合线位于图案化导电层的同一侧。 形成模塑料以封装图案化的导电层，芯片和接合线。 然后，分离模塑料，图案化导电层和图案化阻焊层。

公开(公告)号：US20090047754A1

公开(公告)日：2009-02-19

申请号：US12173936

申请日：2008-07-16

申请人： Yu-Ren Chen ,  Geng-Shin Shen ,  Tz-Cheng Chiu

发明人： Yu-Ren Chen ,  Geng-Shin Shen ,  Tz-Cheng Chiu

IPC分类号： H01L21/56

CPC分类号： H01L21/561 ,  H01L21/568 ,  H01L23/3107 ,  H01L24/19 ,  H01L24/96 ,  H01L24/97 ,  H01L2224/04105 ,  H01L2224/12105 ,  H01L2224/20 ,  H01L2224/92 ,  H01L2924/01033 ,  H01L2924/01075 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/09701 ,  H01L2924/10158 ,  H01L2924/14 ,  H01L2924/181 ,  H01L2924/1815 ,  H01L2924/3511 ,  H01L2224/96 ,  H01L2224/82 ,  H01L2924/00

摘要： A packaging method is disclosed that comprises attaching a plurality of dice, each having a plurality of bonding pads disposed on an active surface, to an adhesive layer on a substrate. A polymer material is formed over at least a portion of both the substrate and the plurality of dice and a molding apparatus is used on the substrate to force the polymer material to substantially fill around the plurality of dice. The molding apparatus is removed to expose a surface of the polymer material and a plurality of cutting streets is formed on an exposed surface of the polymer material. The substrate is removed to expose the active surface of the plurality of dice

摘要翻译： 公开了一种包装方法，其包括将多个具有设置在活性表面上的多个接合焊盘附着到基板上的粘合剂层的芯片。 聚合物材料形成在基底和多个骰子的至少一部分上，并且在基底上使用模塑设备以迫使聚合物材料基本上填充在多个骰子周围。 去除模制设备以暴露聚合物材料的表面，并且在聚合物材料的暴露表面上形成多个切割街道。 去除衬底以暴露多个裸片的活性表面

公开(公告)号：US20080315417A1

公开(公告)日：2008-12-25

申请号：US12201231

申请日：2008-08-29

申请人： Geng-Shin Shen ,  Chun-Ying Lin ,  Shih-Wen Chou

发明人： Geng-Shin Shen ,  Chun-Ying Lin ,  Shih-Wen Chou

IPC分类号： H01L23/498

CPC分类号： H01L24/83 ,  H01L23/3128 ,  H01L23/4951 ,  H01L23/49534 ,  H01L23/49816 ,  H01L23/49822 ,  H01L23/5389 ,  H01L24/27 ,  H01L24/29 ,  H01L24/45 ,  H01L24/48 ,  H01L24/85 ,  H01L24/97 ,  H01L2224/274 ,  H01L2224/29007 ,  H01L2224/2919 ,  H01L2224/32225 ,  H01L2224/45144 ,  H01L2224/48091 ,  H01L2224/4824 ,  H01L2224/73215 ,  H01L2224/83191 ,  H01L2224/83194 ,  H01L2224/83856 ,  H01L2224/85 ,  H01L2224/97 ,  H01L2924/01005 ,  H01L2924/01027 ,  H01L2924/01028 ,  H01L2924/01033 ,  H01L2924/01074 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/0665 ,  H01L2924/07802 ,  H01L2924/14 ,  H01L2924/15311 ,  H01L2924/1532 ,  H01L2924/181 ,  H01L2924/18165 ,  H01L2924/00014 ,  H01L2224/83 ,  H01L2924/00 ,  H01L2924/00012

摘要： A chip package includes a patterned conductive layer, a first solder resist layer, a second solder resist layer, a chip, bonding wires and a molding compound. The patterned conductive layer has a first surface and a second surface opposite to each other. The first solder resist layer is disposed on the first surface. The second solder resist layer is disposed on the second surface, wherein a part of the second surface is exposed by the second solder resist layer. The chip is disposed on the first solder resist layer, wherein the first solder resist layer is disposed between the patterned conductive layer and the chip. The bonding wires are electrically connected to the chip and the patterned conductive layer exposed by the second solder resist layer. The molding compound encapsulates the pattern conductive layer, the first solder resist layer, the second solder resist layer, the chip and the bonding wires.

摘要翻译： 芯片封装包括图案化导电层，第一阻焊层，第二阻焊层，芯片，接合线和模塑料。 图案化导电层具有彼此相对的第一表面和第二表面。 第一阻焊层设置在第一表面上。 第二阻焊层设置在第二表面上，其中第二表面的一部分被第二阻焊层曝光。 芯片设置在第一阻焊层上，其中第一阻焊层设置在图案化的导电层和芯片之间。 接合线电连接到芯片和由第二阻焊层暴露的图案化导电层。 模塑料封装图案导电层，第一阻焊层，第二阻焊层，芯片和接合线。

公开(公告)号：US07446407B2

公开(公告)日：2008-11-04

申请号：US11217978

申请日：2005-08-31

申请人： Chun-Hung Lin ,  Geng-Shin Shen

发明人： Chun-Hung Lin ,  Geng-Shin Shen

IPC分类号： H01L23/12 ,  H01L23/34 ,  H01L23/10 ,  H01L23/31 ,  H01L21/50 ,  H01L21/48 ,  H01L21/44

CPC分类号： H01L23/3114 ,  H01L23/13 ,  H01L23/36 ,  H01L24/48 ,  H01L2224/32225 ,  H01L2224/451 ,  H01L2224/48091 ,  H01L2224/4824 ,  H01L2224/73215 ,  H01L2224/73253 ,  H01L2924/00014 ,  H01L2924/01087 ,  H01L2924/14 ,  H01L2924/15311 ,  H01L2924/16152 ,  H01L2924/00012 ,  H01L2924/00 ,  H01L2224/45099 ,  H01L2224/05599

摘要： A chip package structure includes a substrate, a chip, a first B-stage adhesive, bonding wires, a heat sink and a molding compound. The substrate comprises a first surface, a second surface and a through hole. The chip is arranged on the first surface of the substrate and electrically connected thereto while the through hole of the substrate exposes a portion of the chip. The first B-stage adhesive is arranged between the chip and the first surface of the substrate, and the chip is attached to the substrate through the first B-stage adhesive. The bonding wires are connected between the chip exposed by the through hole and second surface of the substrate. The heat sink is arranged on the first surface of the substrate, covering the chip. The molding compound is arranged on the second surface of the substrate, covering a portion of the substrate and bonding wires.

摘要翻译： 芯片封装结构包括基板，芯片，第一B阶粘合剂，接合线，散热片和模塑料。 基板包括第一表面，第二表面和通孔。 芯片布置在基板的第一表面上并与之电连接，同时基板的通孔暴露芯片的一部分。 第一B级粘合剂布置在芯片和基板的第一表面之间，并且芯片通过第一B级粘合剂附接到基板。 接合线连接在由通孔暴露的芯片和基板的第二表面之间。 散热器布置在基板的第一表面上，覆盖芯片。 模塑料配置在基板的第二表面上，覆盖基板的一部分和接合线。

公开(公告)号：US20080265397A1

公开(公告)日：2008-10-30

申请号：US11872205

申请日：2007-10-15

申请人： Chun-Ying Lin ,  Yu-Tang Pan ,  Shih-Wen Chou ,  Geng-Shin Shen

发明人： Chun-Ying Lin ,  Yu-Tang Pan ,  Shih-Wen Chou ,  Geng-Shin Shen

IPC分类号： H01L23/49

CPC分类号： H01L25/0657 ,  H01L23/3121 ,  H01L24/73 ,  H01L2224/0401 ,  H01L2224/04073 ,  H01L2224/06135 ,  H01L2224/06136 ,  H01L2224/16145 ,  H01L2224/16235 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/48235 ,  H01L2224/4824 ,  H01L2224/4918 ,  H01L2224/731 ,  H01L2224/73204 ,  H01L2224/73215 ,  H01L2224/73265 ,  H01L2224/83102 ,  H01L2224/92125 ,  H01L2225/0651 ,  H01L2225/06513 ,  H01L2225/06517 ,  H01L2225/06527 ,  H01L2225/06582 ,  H01L2225/06589 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2924/00014 ,  H01L2924/00 ,  H01L2924/00012

摘要： A chip stacked package structure and applications are provided, wherein the chip stacked package structure comprises a substrate, a first chip, a patterned circuit layer and a second chip. The substrate has a first surface and an opposite second surface. The first chip with a first active area and an opposite first rear surface is electrically connected to first surface of substrate by a flip chip bonding process. The patterned circuit layer set on the dielectric layer is electrically connected to the substrate via a bonding wire. The second chip set on the patterned circuit layer has a second active area and a plurality of second pads formed on the second active area, wherein the second bonding pad is electrically connected to the patterned circuit layer.

摘要翻译： 提供了芯片堆叠封装结构和应用，其中芯片堆叠封装结构包括衬底，第一芯片，图案化电路层和第二芯片。 衬底具有第一表面和相对的第二表面。 具有第一有源区和相对的第一后表面的第一芯片通过倒装芯片接合工艺电连接到衬底的第一表面。 设置在电介质层上的图案化电路层通过接合线电连接到基板。 设置在图案化电路层上的第二芯片具有形成在第二有源区上的第二有源区和多个第二焊盘，其中第二焊盘与图案化电路层电连接。