公开(公告)号：US09472470B2

公开(公告)日：2016-10-18

申请号：US14564323

申请日：2014-12-09

Applicant: GLOBALFOUNDRIES INC.

Inventor： Kangguo Cheng ,  Ali Khakifirooz ,  Alexander Reznicek ,  Dominic J. Schepis

IPC: H01L21/84 ,  H01L29/66 ,  H01L29/78 ,  H01L29/08 ,  H01L29/04 ,  H01L21/8238 ,  H01L21/8234

CPC classification number: H01L21/845 ,  H01L21/823431 ,  H01L21/823821 ,  H01L29/045 ,  H01L29/0847 ,  H01L29/66545 ,  H01L29/66636 ,  H01L29/66795 ,  H01L29/6681 ,  H01L29/7848 ,  H01L29/785

Abstract: A method including forming fin spacers on opposite sidewalls of a semiconductor fin made from a semiconductor substrate, forming a dielectric layer in direct contact with the fin spacers such that a top surface of the fin and a top surface of the fin spacers remain exposed, recessing a portion of the fin between the fin spacers, removing the fin spacers to create an opening, and epitaxially growing an unmerged source drain region in the opening, where lateral growth of the unmerged source drain region is constrained on opposite sides by the dielectric layer.

Abstract translation: 一种方法，包括在由半导体衬底制成的半导体鳍片的相对侧壁上形成翅片间隔物，形成与翅片间隔件直接接触的电介质层，使得翅片的顶表面和翅片间隔件的顶表面保持暴露，凹陷 翅片间隔件的一部分，去除翅片间隔件以形成开口，并且在开口中外延生长未熔化的源极漏极区域，其中未熔化的源极漏极区域的横向生长通过电介质层约束在相对的两侧。

公开(公告)号：US09455141B2

公开(公告)日：2016-09-27

申请号：US14574533

申请日：2014-12-18

Applicant: GLOBALFOUNDRIES INC.

Inventor： Kanggou Cheng ,  Ali Khakifirooz ,  Alexander Reznicek ,  Dominic J. Schepis

IPC: H01L21/02 ,  H01L29/66 ,  H01L29/161 ,  H01L29/06

CPC classification number: H01L21/02532 ,  H01L21/02422 ,  H01L21/0245 ,  H01L21/02587 ,  H01L21/02612 ,  H01L21/02664 ,  H01L29/0653 ,  H01L29/0657 ,  H01L29/161 ,  H01L29/66795

Abstract: Embodiments of the invention include a method for fabricating a SiGe fin and the resulting structure. A SOI substrate is provided, including at least a silicon layer on top of a BOX. At least one fin upon a thin layer of silicon and a hard mask layer over the at least one fin is formed using the silicon layer on top of the BOX. A SiGe layer is epitaxially grown from exposed portions of the fin and the thin layer of silicon. Spacers are formed on sidewalls of the hard mask. Regions of the SiGe layer and the thin layer of silicon not protected by the spacers are etched, such that portions of the BOX are exposed. A condensation process converts the fin to SiGe and to convert the SiGe layer to oxide. The hard mask, the spacers, and the oxide layer are removed.

Abstract translation: 本发明的实施例包括制造SiGe鳍片的方法和所得到的结构。 提供SOI衬底，其至少包括在BOX顶部的硅层。 使用BOX顶部的硅层，在至少一个散热片上的薄层硅层和硬掩模层上形成至少一个鳍片。 SiGe层从翅片和薄层硅的暴露部分外延生长。 垫片形成在硬掩模的侧壁上。 SiGe层的区域和未被间隔物保护的硅的薄层被蚀刻，使得BOX的部分被暴露。 冷凝过程将翅片转换成SiGe并将SiGe层转化为氧化物。 去除硬掩模，间隔物和氧化物层。

公开(公告)号：US09443948B2

公开(公告)日：2016-09-13

申请号：US14532122

申请日：2014-11-04

Applicant: GlobalFoundries Inc.

Inventor： Kangguo Cheng ,  Bruce B. Doris ,  Pouya Hashemi ,  Ali Khakifirooz ,  Alexander Reznicek

IPC: H01L21/8238 ,  H01L29/423 ,  H01L29/06 ,  H01L29/66 ,  H01L51/00 ,  H01L29/775 ,  H01L29/49 ,  H01L29/51

CPC classification number: H01L29/42392 ,  H01L21/8238 ,  H01L21/82385 ,  H01L29/0649 ,  H01L29/0669 ,  H01L29/0673 ,  H01L29/0676 ,  H01L29/0847 ,  H01L29/1033 ,  H01L29/495 ,  H01L29/4966 ,  H01L29/4983 ,  H01L29/51 ,  H01L29/517 ,  H01L29/518 ,  H01L29/66439 ,  H01L29/66545 ,  H01L29/775 ,  H01L29/78603 ,  H01L29/78606 ,  H01L29/78696 ,  H01L51/0048

Abstract: A method for fabricating a semiconductor device comprises forming a nanowire on an insulator layer at a surface of a substrate; forming a dummy gate over a portion of the nanowire and a portion of the insulator layer; forming recesses in the insulator layer on opposing sides of the dummy gate; forming spacers on opposing sides of the dummy gate; forming source regions and drain regions in the recesses in the insulator layer on opposing sides of the dummy gate; depositing an interlayer dielectric on the source regions and the drain regions; removing the dummy gate to form a trench; removing the insulator layer under the nanowire such that a width of the trench underneath the nanowire is equal to or less than a distance between the spacers; and forming a replacement gate in the trench.

公开(公告)号：US20160225766A1

公开(公告)日：2016-08-04

申请号：US15096681

申请日：2016-04-12

Applicant: GLOBALFOUNDRIES INC.

Inventor： Kangguo Cheng ,  Ali Khakifirooz ,  Alexander Reznicek ,  Charan Veera Venkata Satya Surisetty

IPC: H01L27/088 ,  H01L29/51 ,  H01L29/49

CPC classification number: H01L27/0886 ,  H01L21/76837 ,  H01L21/76897 ,  H01L21/823468 ,  H01L29/41766 ,  H01L29/4983 ,  H01L29/51 ,  H01L29/517 ,  H01L29/518 ,  H01L29/6653 ,  H01L29/66545 ,  H01L29/66795

Abstract: A semiconductor device includes gates and a low-k spacer. The low-k spacer includes low-k spacer portions formed upon the gate sidewalls and a low-k spacer portion formed upon a top surface of an underlying substrate adjacent to the gates. When a structure has previously undergone a gate processing fabrication stage, the gates and at least a portion of the top surface of the substrate may be exposed thereby allowing the formation of the low-k spacer. This exposure may include removing any original gate spacers, removing an original liner formed upon the original spacers, and removing any original fill material formed upon the liner.

公开(公告)号：US20160181105A1

公开(公告)日：2016-06-23

申请号：US14572975

申请日：2014-12-17

Applicant: GLOBALFOUNDRIES INC.

Inventor： Kangguo Cheng ,  Ali Khakifirooz ,  Alexander Reznicek ,  Dominic J. Schepis

IPC: H01L21/225 ,  H01L29/78 ,  H01L29/06 ,  H01L21/8234 ,  H01L29/161

CPC classification number: H01L29/785 ,  H01L21/18 ,  H01L21/845 ,  H01L27/1211 ,  H01L29/161

Abstract: Constructing an SiGe fin by: (i) providing an intermediate sub-assembly including a silicon-containing base layer and a silicon-containing first fin structure extending in an upwards direction from the base layer; (ii) refining the sub-assembly by covering at least a portion of the top surface of the base layer and at least a portion of the first and second lateral surfaces of the first fin structure with a pre-thermal-oxidation layer that includes Silicon-Germanium (SiGe); and (iii) further refining the sub-assembly by thermally oxidizing the pre-thermal oxidation layer to migrate Ge content from the pre-thermal-oxidation layer into at least a portion of the base layer and at least a portion of first fin structure.

Abstract translation: 通过以下步骤构造SiGe翅片：（i）提供包括从基底层向上方延伸的含硅基底层和含硅的第一翅片结构的中间子组件; （ii）通过用包括硅的预热氧化层覆盖基层的顶表面的至少一部分和第一鳍结构的第一和第二侧表面的至少一部分来精炼子组件 锗（SiGe）; 和（iii）通过热氧化预热氧化层以使Ge含量从预热氧化层迁移到基层的至少一部分和第一翅片结构的至少一部分中，进一步细化子组件。

公开(公告)号：US09362309B2

公开(公告)日：2016-06-07

申请号：US14528266

申请日：2014-10-30

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Thomas N. Adam ,  Kangguo Cheng ,  Ali Khakifirooz ,  Alexander Reznicek

IPC: H01L21/84 ,  H01L27/12 ,  H01L21/8234 ,  H01L27/088 ,  H01L21/02 ,  H01L29/78 ,  H01L27/11

CPC classification number: H01L27/1211 ,  H01L21/02609 ,  H01L21/02634 ,  H01L21/823431 ,  H01L21/845 ,  H01L27/0886 ,  H01L27/1104 ,  H01L29/7855

Abstract: An improved finFET and method of fabrication is disclosed. Embodiments of the present invention take advantage of the different epitaxial growth rates of {110} and {100} silicon. Fins are formed that have {110} silicon on the fin tops and {100} silicon on the long fin sides (sidewalls). The lateral epitaxial growth rate is faster than the vertical epitaxial growth rate. The resulting merged fins have a reduced merged region in the vertical dimension, which reduces parasitic capacitance. Other fins are formed with {110} silicon on the fin tops and also {110} silicon on the long fin sides. These fins have a slower epitaxial growth rate than the {100} side fins, and remain unmerged in a semiconductor integrated circuit, such as an SRAM circuit.

公开(公告)号：US09324796B2

公开(公告)日：2016-04-26

申请号：US14751646

申请日：2015-06-26

Applicant: GLOBALFOUNDRIES INC.

Inventor： Kangguo Cheng ,  Bruce B. Doris ,  Pouya Hashemi ,  Ali Khakifirooz ,  Alexander Reznicek

IPC: H01L21/8238 ,  H01L29/06 ,  H01L29/66 ,  H01L51/00 ,  H01L29/49 ,  H01L29/775 ,  H01L29/423 ,  H01L29/51 ,  H01L29/10 ,  H01L29/786 ,  H01L29/08

CPC classification number: H01L29/42392 ,  H01L21/8238 ,  H01L21/82385 ,  H01L29/0649 ,  H01L29/0669 ,  H01L29/0673 ,  H01L29/0676 ,  H01L29/0847 ,  H01L29/1033 ,  H01L29/495 ,  H01L29/4966 ,  H01L29/4983 ,  H01L29/51 ,  H01L29/517 ,  H01L29/518 ,  H01L29/66439 ,  H01L29/66545 ,  H01L29/775 ,  H01L29/78603 ,  H01L29/78606 ,  H01L29/78696 ,  H01L51/0048

Abstract: A method for fabricating a semiconductor device comprises forming a nanowire on an insulator layer at a surface of a substrate; forming a dummy gate over a portion of the nanowire and a portion of the insulator layer; forming recesses in the insulator layer on opposing sides of the dummy gate; forming spacers on opposing sides of the dummy gate; forming source regions and drain regions in the recesses in the insulator layer on opposing sides of the dummy gate; depositing an interlayer dielectric on the source regions and the drain regions; removing the dummy gate to form a trench; removing the insulator layer under the nanowire such that a width of the trench underneath the nanowire is equal to or less than a distance between the spacers; and forming a replacement gate in the trench.

公开(公告)号：US09293532B2

公开(公告)日：2016-03-22

申请号：US14751542

申请日：2015-06-26

Applicant: GLOBALFOUNDRIES INC.

Inventor： Kangguo Cheng ,  Bruce B. Doris ,  Pouya Hashemi ,  Ali Khakifirooz ,  Alexander Reznicek

IPC: H01L21/8238 ,  H01L29/06 ,  H01L29/66 ,  H01L51/00 ,  H01L29/49 ,  H01L29/775 ,  H01L29/423 ,  H01L29/51 ,  H01L29/10 ,  H01L29/786 ,  H01L29/08

CPC classification number: H01L29/42392 ,  H01L21/8238 ,  H01L21/82385 ,  H01L29/0649 ,  H01L29/0669 ,  H01L29/0673 ,  H01L29/0676 ,  H01L29/0847 ,  H01L29/1033 ,  H01L29/495 ,  H01L29/4966 ,  H01L29/4983 ,  H01L29/51 ,  H01L29/517 ,  H01L29/518 ,  H01L29/66439 ,  H01L29/66545 ,  H01L29/775 ,  H01L29/78603 ,  H01L29/78606 ,  H01L29/78696 ,  H01L51/0048

Abstract: A method for fabricating a semiconductor device comprises forming a nanowire on an insulator layer at a surface of a substrate; forming a dummy gate over a portion of the nanowire and a portion of the insulator layer; forming recesses in the insulator layer on opposing sides of the dummy gate; forming spacers on opposing sides of the dummy gate; forming source regions and drain regions in the recesses in the insulator layer on opposing sides of the dummy gate; depositing an interlayer dielectric on the source regions and the drain regions; removing the dummy gate to form a trench; removing the insulator layer under the nanowire such that a width of the trench underneath the nanowire is equal to or less than a distance between the spacers; and forming a replacement gate in the trench.

公开(公告)号：US09276118B2

公开(公告)日：2016-03-01

申请号：US14640851

申请日：2015-03-06

Applicant: GLOBALFOUNDRIES INC.

Inventor： Pranita Kerber ,  Qiqing C. Ouyang ,  Alexander Reznicek

IPC: H01L27/01 ,  H01L29/78 ,  H01L29/66 ,  H01L29/08

CPC classification number: H01L29/785 ,  H01L29/0847 ,  H01L29/66795 ,  H01L29/7853

Abstract: A method for manufacturing a fin field-effect transistor (FinFET) device, comprises forming a plurality of fins on a substrate, forming a plurality of gate regions on portions of the fins, wherein the gate regions are spaced apart from each other, forming spacers on each respective gate region, epitaxially growing a first epitaxy region on each of the fins, stopping growth of the first epitaxy regions prior to merging of the first epitaxy regions between adjacent fins, forming a dielectric layer on the substrate including the fins and first epitaxy regions, removing the dielectric layer and first epitaxy regions from the fins at one or more portions between adjacent gate regions to form one or more contact area trenches, and epitaxially growing a second epitaxy region on each of the fins in the one or more contact area trenches, wherein the second epitaxy regions on adjacent fins merge with each other.

Abstract translation: 一种用于制造鳍状场效应晶体管（FinFET）器件的方法，包括在衬底上形成多个鳍片，在鳍片的部分上形成多个栅极区域，其中栅极区域彼此间隔开，形成间隔物 在每个相应的栅极区域上，在每个鳍片上外延生长第一外延区域，在相邻鳍片之间的第一外延区域合并之前停止第一外延区域的生长，在包括鳍片的衬底上形成介电层，并且第一外延 在相邻栅极区之间的一个或多个部分处从所述鳍片去除所述电介质层和所述第一外延区域，以形成一个或多个接触区域沟槽，以及在所述一个或多个接触区域中的所述鳍片上外延生长第二外延区域 沟槽，其中相邻鳍片上的第二外延区域彼此合并。

公开(公告)号：US09224822B2

公开(公告)日：2015-12-29

申请号：US14023007

申请日：2013-09-10

Applicant: GLOBALFOUNDRIES INC.

Inventor： Kangguo Cheng ,  Pouya Hashemi ,  Ali Khakifirooz ,  Alexander Reznicek

IPC: H01L21/20 ,  H01L21/36 ,  H01L29/36 ,  H01L29/161 ,  H01L29/78 ,  H01L29/66 ,  H01L21/02

CPC classification number: H01L29/36 ,  H01L21/02529 ,  H01L21/02532 ,  H01L29/1054 ,  H01L29/161 ,  H01L29/66795 ,  H01L29/785

Abstract: A layer of a silicon germanium alloy containing 30 atomic percent or greater germanium and containing substitutional carbon is grown on a surface of a semiconductor layer. The presence of the substitutional carbon in the layer of silicon germanium alloy compensates the strain of the silicon germanium alloy, and suppresses defect formation. Placeholder semiconductor fins are then formed to a desired dimension within the layer of silicon germanium alloy and the semiconductor layer. The placeholder semiconductor fins will relax for the most part, while maintaining strain in a lengthwise direction. An anneal is then performed which may either remove the substitutional carbon from each placeholder semiconductor fin or move the substitutional carbon into interstitial sites within the lattice of the silicon germanium alloy. Free-standing permanent semiconductor fins containing 30 atomic percent or greater germanium, and strain in the lengthwise direction are provided.

Abstract translation: 在半导体层的表面上生长含有30原子％以上的锗并含有取代碳的硅锗合金层。 硅锗合金层中的取代碳的存在补偿了硅锗合金的应变，并抑制了缺陷的形成。 然后将占位半导体散热片形成为硅锗合金层和半导体层内所需的尺寸。 占位半导体鳍片大部分放松，同时保持长度方向的应变。 然后进行退火，其可以从每个占位符半导体鳍去除取代的碳，或者将取代的碳移动到硅锗合金的晶格内的间隙位置。 提供含有30原子％以上的锗的独立的永久性半导体散热片，并且在长度方向上具有应变。