公开(公告)号：US20160307849A1

公开(公告)日：2016-10-20

申请号：US15095650

申请日：2016-04-11

Applicant: Infineon Technologies AG

Inventor： Thorsten Meyer ,  Stephan Senn

IPC: H01L23/532 ,  H01L29/78 ,  H01L29/66 ,  H01L21/768 ,  H01L21/8234 ,  H01L27/088 ,  H01L29/40

CPC classification number: H01L23/53271 ,  H01L27/0922 ,  H01L29/407 ,  H01L29/66674 ,  H01L29/66734 ,  H01L29/78 ,  H01L29/7801 ,  H01L29/7811 ,  H01L29/7813

Abstract: The present disclosure relates to a semiconductor device, comprising a semiconductor substrate; a trench extending into the semiconductor substrate, wherein the trench is partly filled with an electrically conductive structure insulated from the semiconductor substrate; a polysilicon or amorphous silicon routing structure laterally bridging the trench; and an insulation layer between the trench and the routing structure.

Abstract translation: 本公开涉及一种半导体器件，包括半导体衬底; 延伸到所述半导体衬底中的沟槽，其中所述沟槽部分地填充有与所述半导体衬底绝缘的导电结构; 横向桥接沟槽的多晶硅或非晶硅布线结构; 以及沟槽和布线结构之间的绝缘层。

公开(公告)号：US20160197070A1

公开(公告)日：2016-07-07

申请号：US15051105

申请日：2016-02-23

Applicant: Infineon Technologies AG

Inventor： Markus Zundel ,  Andreas Meiser ,  Hans-Peter Lang ,  Thorsten Meyer ,  Peter Irsigler

IPC: H01L27/06 ,  H01L29/45 ,  H01L29/423 ,  H01L29/417 ,  H01L29/78 ,  H01L29/861

CPC classification number: H01L29/7813 ,  H01L21/02 ,  H01L21/743 ,  H01L21/762 ,  H01L21/76224 ,  H01L21/823418 ,  H01L21/823475 ,  H01L23/48 ,  H01L27/0629 ,  H01L27/0694 ,  H01L29/06 ,  H01L29/0657 ,  H01L29/407 ,  H01L29/417 ,  H01L29/41741 ,  H01L29/41766 ,  H01L29/4236 ,  H01L29/456 ,  H01L29/66477 ,  H01L29/66727 ,  H01L29/66734 ,  H01L29/78 ,  H01L29/7803 ,  H01L29/7827 ,  H01L29/7845 ,  H01L29/861 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A semiconductor device includes a semiconductor body having first and second opposing sides. Contact trenches extend, from the first and second sides, through a dielectric and into the semiconductor body. The contact trenches include conductive material electrically connected to the semiconductor body via sidewalls. The contact trenches include a first contact trench extending through a first dielectric and into the semiconductor body at the first side, the first contact trench including a first conductive material electrically connected to the semiconductor body adjoining the first contact trench, a second contact trench extending through a second dielectric and into the semiconductor body at the second side, the second contact trench including a second conductive material, a first contact pattern surrounded by the first dielectric at the first side, and a second contact pattern surrounded by the second dielectric at the second side.

Abstract translation: 半导体器件包括具有第一和第二相对侧的半导体本体。 接触沟槽从第一侧和第二侧延伸穿过电介质并进入半导体本体。 接触沟槽包括通过侧壁电连接到半导体本体的导电材料。 接触沟槽包括延伸穿过第一电介质并在第一侧进入半导体本体的第一接触沟槽，第一接触沟槽包括电连接到邻接第一接触沟槽的半导体本体的第一导电材料，延伸穿过第二接触沟槽 第二电介质并且在第二侧进入半导体本体，第二接触沟槽包括第二导电材料，由第一侧面处的第一电介质围绕的第一接触图案和在第二侧被第二电介质包围的第二接触图案 侧。

公开(公告)号：US09355909B2

公开(公告)日：2016-05-31

申请号：US14148776

申请日：2014-01-07

Applicant: Infineon Technologies AG

Inventor： Thorsten Meyer ,  Stefan Decker ,  Norbert Krischke ,  Christoph Kadow

IPC: H01L27/148 ,  H01L29/768 ,  H01L21/8234 ,  H01L21/265 ,  H01L21/266 ,  H01L21/8238 ,  H01L27/088 ,  H01L29/10 ,  H01L29/66 ,  H01L29/78

CPC classification number: H01L29/105 ,  H01L21/26513 ,  H01L21/266 ,  H01L21/823412 ,  H01L21/823807 ,  H01L27/088 ,  H01L29/4236 ,  H01L29/66537 ,  H01L29/78

Abstract: An integrated circuit having field effect transistors and manufacturing method. One embodiment provides an integrated circuit including a first FET and a second FET. At least one of source, drain, gate of the first FET is electrically connected to the corresponding one of source, drain, gate of the second FET. At least one further of source, drain, gate of the first FET and the corresponding one further of source, drain, gate of the second FET are connected to a circuit element, respectively. A dopant concentration of a body along a channel of each of the first and second FETs has a peak at a peak location within the channel.

Abstract translation: 一种具有场效应晶体管和制造方法的集成电路。 一个实施例提供了包括第一FET和第二FET的集成电路。 第一FET的源极，漏极，栅极中的至少一个电连接到第二FET的源极，漏极，栅极中的相应一个栅极。 第一FET的源极，漏极，栅极以及第二FET的源极，漏极，栅极之间的至少另外的栅极分别连接到电路元件。 沿着第一和第二FET中的每一个的通道的主体的掺杂剂浓度在通道内的峰值位置处具有峰值。

公开(公告)号：US09123801B2

公开(公告)日：2015-09-01

申请号：US14027570

申请日：2013-09-16

Applicant: Infineon Technologies AG

Inventor： Andreas Meiser ,  Till Schloesser ,  Thorsten Meyer

IPC: H01L29/66 ,  H01L29/78

CPC classification number: H01L29/66704 ,  H01L21/28008 ,  H01L21/76 ,  H01L21/761 ,  H01L21/823487 ,  H01L27/088 ,  H01L29/404 ,  H01L29/407 ,  H01L29/66659 ,  H01L29/66734 ,  H01L29/7813 ,  H01L29/7835

Abstract: A semiconductor device includes a transistor in a semiconductor substrate having a first main surface. The transistor includes a source region, a drain region, a channel region, a drift zone, and a gate electrode adjacent to at least two sides of the channel region. The channel region and the drift zone are disposed along a first direction parallel to the first main surface, between the source region and the drain region. The semiconductor device further includes a conductive layer beneath the gate electrode and insulated from the gate electrode.

Abstract translation: 半导体器件包括具有第一主表面的半导体衬底中的晶体管。 晶体管包括源极区域，漏极区域，沟道区域，漂移区域和与沟道区域的至少两侧相邻的栅电极。 沟道区域和漂移区沿着平行于第一主表面的第一方向，在源极区域和漏极区域之间设置。 半导体器件还包括在栅电极下方并与栅电极绝缘的导电层。

公开(公告)号：US20150076590A1

公开(公告)日：2015-03-19

申请号：US14027570

申请日：2013-09-16

Applicant: Infineon Technologies AG

Inventor： Andreas Meiser ,  Till Schloesser ,  Thorsten Meyer

IPC: H01L29/78 ,  H01L29/66

CPC classification number: H01L29/66704 ,  H01L21/28008 ,  H01L21/76 ,  H01L21/761 ,  H01L21/823487 ,  H01L27/088 ,  H01L29/404 ,  H01L29/407 ,  H01L29/66659 ,  H01L29/66734 ,  H01L29/7813 ,  H01L29/7835

Abstract: A semiconductor device includes a transistor in a semiconductor substrate having a first main surface. The transistor includes a source region, a drain region, a channel region, a drift zone, and a gate electrode adjacent to at least two sides of the channel region. The channel region and the drift zone are disposed along a first direction parallel to the first main surface, between the source region and the drain region. The semiconductor device further includes a conductive layer beneath the gate electrode and insulated from the gate electrode.

Abstract translation: 半导体器件包括具有第一主表面的半导体衬底中的晶体管。 晶体管包括源极区域，漏极区域，沟道区域，漂移区域和与沟道区域的至少两侧相邻的栅电极。 沟道区域和漂移区沿着平行于第一主表面的第一方向，在源极区域和漏极区域之间设置。 半导体器件还包括在栅电极下方并与栅电极绝缘的导电层。

公开(公告)号：US08815686B2

公开(公告)日：2014-08-26

申请号：US13803291

申请日：2013-03-14

Applicant: Infineon Technologies AG

Inventor： Franz Hirler ,  Uwe Wahl ,  Thorsten Meyer ,  Michael Rüb ,  Armin Willmeroth ,  Markus Schmitt ,  Carolin Tolksdorf ,  Carsten Schaeffer

IPC: H01L21/336

CPC classification number: H01L29/66689 ,  H01L21/26586 ,  H01L29/0696 ,  H01L29/1045 ,  H01L29/1095 ,  H01L29/41758 ,  H01L29/4236 ,  H01L29/42368 ,  H01L29/66666 ,  H01L29/66704 ,  H01L29/78 ,  H01L29/7825

Abstract: A method for production of doped semiconductor regions in a semiconductor body of a lateral trench transistor includes forming a trench in the semiconductor body and introducing dopants into at least one area of the semiconductor body that is adjacent to the trench, by carrying out a process in which dopants enter the at least one area through inner walls of the trench.

Abstract translation: 在横向沟槽晶体管的半导体本体中制造掺杂半导体区域的方法包括：在半导体本体中形成沟槽，并且通过在半导体本体中进行工艺，将掺杂物引入与沟槽相邻的半导体本体的至少一个区域中 所述掺杂剂通过沟槽的内壁进入至少一个区域。

公开(公告)号：US20140120673A1

公开(公告)日：2014-05-01

申请号：US14148776

申请日：2014-01-07

Applicant: Infineon Technologies AG

Inventor： Thorsten Meyer ,  Stefan Decker ,  Norbert Krischke ,  Christoph Kadow

IPC: H01L21/8234

CPC classification number: H01L29/105 ,  H01L21/26513 ,  H01L21/266 ,  H01L21/823412 ,  H01L21/823807 ,  H01L27/088 ,  H01L29/4236 ,  H01L29/66537 ,  H01L29/78

Abstract: An integrated circuit having field effect transistors and manufacturing method. One embodiment provides an integrated circuit including a first FET and a second FET. At least one of source, drain, gate of the first FET is electrically connected to the corresponding one of source, drain, gate of the second FET. At least one further of source, drain, gate of the first FET and the corresponding one further of source, drain, gate of the second FET are connected to a circuit element, respectively. A dopant concentration of a body along a channel of each of the first and second FETs has a peak at a peak location within the channel.

Abstract translation: 一种具有场效应晶体管和制造方法的集成电路。 一个实施例提供了包括第一FET和第二FET的集成电路。 第一FET的源极，漏极，栅极中的至少一个电连接到第二FET的源极，漏极，栅极中的相应一个栅极。 第一FET的源极，漏极，栅极以及第二FET的源极，漏极，栅极之间的至少另外的栅极分别连接到电路元件。 沿着第一和第二FET中的每一个的通道的主体的掺杂剂浓度在通道内的峰值位置处具有峰值。