公开(公告)号：US20210208659A1

公开(公告)日：2021-07-08

申请号：US17207299

申请日：2021-03-19

Applicant: Intel Corporation

Inventor： Alexander Gendler ,  Adwait Purandare ,  Ankush Varma ,  Nazar Haider ,  Daniela Kaufman ,  Gilad Bomstein ,  Shlomo Attias ,  Amit Gabai ,  Ariel Szapiro

IPC: G06F1/324 ,  G06F21/55 ,  G06F1/28

Abstract: An adaptive or dynamic power virus control scheme (hardware and/or software) that dynamically adjusts maximum dynamic capacitance (CdynMax) and corresponding maximum frequency (POnMax) setting per application executed on a processor core. A power management unit monitors telemetry such as a number of throttled cycles due to CdynMax threshold excursions cycles for the processor core and a cost of average cycle Cdyn cost for the processor core. As the number of throttling cycles increases for the processor core, the aCode firmware of the power management unit decides to increase the Cdyn level or threshold for that core (e.g., to make the threshold less aggressive). As the average Cdyn cost over a number of cycles becomes lower than a threshold, aCode adjusts the threshold to a lower threshold (e.g., more aggressive threshold) and lower Cdyn.

公开(公告)号：US11016556B2

公开(公告)日：2021-05-25

申请号：US16513267

申请日：2019-07-16

Applicant: INTEL CORPORATION

Inventor： Alexander Gendler ,  Doron Rajwan ,  Tal Kuzi ,  Dean Mulla ,  Ariel Szapiro ,  Nir Tell

IPC: G06F1/32 ,  G06F1/3296 ,  G06F1/3206 ,  G06F1/324

Abstract: A parallel multi-step power management flow apparatus and method for using the same are disclosed. In one embodiment, an integrated circuit comprises a plurality of processing entities to execute operations, a power controller coupled to the plurality of processing entities to control power management for the plurality of processing entities, and a plurality of agents, where each of the plurality of agents is operable to perform a power control flow for one of the processing entities by separately scheduling, using a scheduler, and executing a plurality of power control flow phases in response to a plurality of requests received from the power controller, and each agent is operable to send a plurality of acknowledgements, one acknowledgement for each phase, upon completion of the plurality of power control flow phases.

公开(公告)号：US20210064110A1

公开(公告)日：2021-03-04

申请号：US16633176

申请日：2018-08-27

Applicant: Intel Corporation

Inventor： Alexander Gendler ,  Krishnakanth V. Sistla ,  Ankush Varma ,  Ariel Szapiro

IPC: G06F1/28 ,  G06F9/38

Abstract: In an embodiment, a processor includes a power control unit, a master processing engine, a set of slave processing engines, and a voltage regulator. The master processing engine is to, in response to a receipt of a change message from the power control unit, control the voltage regulator to adjust a voltage level provided to the master processing engine and the set of slave processing engines. Other embodiments are described and claimed.

公开(公告)号：US10936041B2

公开(公告)日：2021-03-02

申请号：US16369793

申请日：2019-03-29

Applicant: Intel Corporation

Inventor： Alexander Gendler ,  Igor Yanover ,  Gavri Berger ,  Edo Hachamo ,  Elkana Korem ,  Hanan Shomroni ,  Daniela Kaufman ,  Lev Makovsky ,  Haim Granot

IPC: G06F1/32 ,  G06F1/324 ,  G06F1/3206

Abstract: In an embodiment, a processor includes processing cores to execute instructions; and throttling logic. The throttling logic is to: determine an average capacitance score for execution events in a sliding window; perform frequency throttling when the average capacitance score exceeds a throttling threshold; determine a count of frequency throttling instances; and in response to a determination that the count of frequency throttling instances exceeds a maximum throttling value, increase the throttling threshold and concurrently reduce a baseline frequency. Other embodiments are described and claimed.

公开(公告)号：US20200333867A1

公开(公告)日：2020-10-22

申请号：US16836686

申请日：2020-03-31

Applicant: Intel Corporation

Inventor： Alexander Gendler ,  Efraim Rotem ,  Nir Rosenzweig ,  Krishnakanth V. Sistla ,  Ashish V. Choubal ,  Ankush Varma

IPC: G06F1/324 ,  G06F1/3206 ,  G06F1/3234 ,  G06F1/3287 ,  G06F1/3296 ,  G06F1/26

Abstract: Apparatuses, methods and storage medium associated with current control for a multicore processor are disclosed herein. In embodiments, a multicore processor may include a plurality of analog current comparators, each analog current comparator to measure current utilization by a corresponding one of the cores of the multicore processor. The multicore processor may include one or more processors, devices, and/or circuitry to cause the cores to individually throttle based on measurements from the corresponding analog current comparators. In some embodiments, a memory device of the multicore processor may store instructions executable to operate a plurality power management agents to determine whether to send throttle requests based on a plurality of histories of the current measurements of the cores, respectively.

公开(公告)号：US10809790B2

公开(公告)日：2020-10-20

申请号：US15638573

申请日：2017-06-30

Applicant: Intel Corporation

Inventor： Yiftach Gilad ,  Ariel Szapiro ,  Elkana Korem ,  Alexander Gendler

IPC: G06F1/32 ,  G06F1/324 ,  G06F1/08 ,  G06F1/3296 ,  H03K5/133 ,  H03K19/003 ,  G11C29/02 ,  G11C7/22 ,  G11C5/14 ,  H03K5/00

Abstract: Apparatus and methods are provided for improving yield and frequency performance of integrated circuit processors, such as multiple-core processors. In an example, an apparatus can include a plurality of clock buffers, each clock buffer of the plurality of clock buffers configured to receive a first clock signal and distribute a plurality of second clock signals, a one-time programmable locate critical path mechanism configured provide a plurality of indications to enable or disable a delay of each clock buffer of the plurality of clock buffers, and a power management control circuit configured to over-ride one or more of the plurality of indications in a first non-test mode of operation of the apparatus and to not over-ride the one or more indications in a second non-test mode of operation of the apparatus.

公开(公告)号：US20190205061A1

公开(公告)日：2019-07-04

申请号：US15858878

申请日：2017-12-29

Applicant: Intel Corporation

Inventor： Eliezer Weissmann ,  Alexander Gendler ,  Efraim Rotem ,  Moshe Cohen ,  Asit K. Mallick ,  Jason W. Brandt ,  Kameswar Subramaniam ,  Nathan Fellman ,  Hisham Shafi

IPC: G06F3/06 ,  G06F9/30

CPC classification number: G06F3/0659 ,  G06F3/0611 ,  G06F3/0673 ,  G06F9/30098 ,  G06F9/4406 ,  G06F9/45558 ,  G06F2009/45583

Abstract: Processor, method, and system for reducing latency in accessing remote registers is described herein. One embodiment of a processor includes one or more remote registers and remote register access circuitry. The remote register access circuitry is to detect a request from the requestor to access a first register of the one or more remote registers, access to the first register in accordance to the request without the requestor having to wait for completion of the access, and provide a notification accessible to the requestor upon completion of the access to the first register of the one or more remote registers.

公开(公告)号：US20190041950A1

公开(公告)日：2019-02-07

申请号：US15938268

申请日：2018-03-28

Applicant: Intel Corporation

Inventor： Michael W. Chynoweth ,  Rajshree Chabukswar ,  Eliezer Weissmann ,  Jason W. Brandt ,  Alexander Gendler ,  Ahmad Yasin ,  Patrick Konsor ,  Sneha Gohad ,  William Freelove

IPC: G06F1/32 ,  G06F12/1045 ,  G06F11/34

Abstract: In one embodiment, a processor includes one or more cores including a cache memory hierarchy; a performance monitor coupled to the one or more cores, the performance monitor to monitor performance of the one or more cores, the performance monitor to calculate pipeline cost metadata based at least in part on count information associated with the cache memory hierarchy; and a power controller coupled to the performance monitor, the power controller to receive the pipeline cost metadata and determine a low power state for the one or more cores to enter based at least in part on the pipeline cost metadata. Other embodiments are described and claimed.

公开(公告)号：US10114435B2

公开(公告)日：2018-10-30

申请号：US14138558

申请日：2013-12-23

Applicant: Intel Corporation

Inventor： Alexander Gendler

IPC: G06F1/00 ,  G06F1/26 ,  G06F1/32

Abstract: In an embodiment, a processor includes a first core that includes an execution unit, counter logic, and control logic. The counter logic is to determine a first sum of power weights of a first plurality of instructions to be executed by the execution unit in a first time period, where each power weight is assigned to a corresponding instruction and each power weight is determined independent of an instruction width of the corresponding instruction. The control logic is to request a first current protection license based on the first sum of power weights. Other embodiments are described and claimed.

公开(公告)号：US20180181401A1

公开(公告)日：2018-06-28

申请号：US15886313

申请日：2018-02-01

Applicant: Intel Corporation

Inventor： Alexander Gendler ,  Larisa Novakovsky ,  Ariel Szapiro

IPC: G06F9/38 ,  G06F1/32 ,  G06F1/26

CPC classification number: G06F9/3802 ,  G06F1/26 ,  G06F1/3206 ,  G06F1/324 ,  G06F1/3243 ,  G06F1/3296 ,  G06F9/3881 ,  Y02D10/126 ,  Y02D10/152 ,  Y02D10/172 ,  Y02D50/20

Abstract: In one embodiment, a processor includes: a core to execute instructions, the core including a plurality of mailbox storages and a trust table to store a trust indicator for each of the plurality of mailbox storages; a first core perimeter logic coupled to the core and including a first storage to store state information of the core when the core is in a low power state; and a second core perimeter logic coupled to the first core perimeter logic and the core, the second core perimeter logic including a second storage to store the state information of the core when the first core perimeter logic is in a low power state. Other embodiments are described and claimed.