公开(公告)号：US11158543B2

公开(公告)日：2021-10-26

申请号：US16506339

申请日：2019-07-09

Applicant: International Business Machines Corporation

Inventor： Heng Wu ,  Su Chen Fan ,  Ruilong Xie ,  Huai Huang

IPC: H01L21/8238 ,  H01L27/092 ,  H01L29/08 ,  H01L29/45 ,  H01L29/78 ,  H01L21/265 ,  H01L21/324 ,  H01L29/66 ,  H01L21/285

Abstract: A method for manufacturing a semiconductor device includes forming a first vertical transistor structure in a first device region on a substrate, and forming a second vertical transistor structure in a second device region on the substrate. The first vertical transistor structure includes a first plurality of fins, and the second vertical transistor structure includes a second plurality of fins. A plurality of first source/drain regions are grown from upper portions of the first plurality of fins, and a contact liner layer is formed on the first source/drain regions. The method further includes forming a plurality of first silicide portions from the contact liner layer on the first source/drain regions, and forming a plurality of second silicide portions on a plurality of second source/drain regions extending from upper portions of the second plurality of fins. The second silicide portions have a different composition than the first silicide portions.

公开(公告)号：US20210296580A1

公开(公告)日：2021-09-23

申请号：US16821660

申请日：2020-03-17

Applicant: International Business Machines Corporation

Inventor： Tian Shen ,  Ruilong Xie ,  Kevin W. Brew ,  Heng Wu ,  Jingyun Zhang

IPC: H01L45/00

Abstract: A phase change material switch includes a phase change layer disposed on a metal liner. A gate dielectric layer is disposed on the phase change layer. A metal gate liner is disposed on the gate dielectric layer.

公开(公告)号：US11075334B2

公开(公告)日：2021-07-27

申请号：US16692766

申请日：2019-11-22

Applicant: International Business Machines Corporation

Inventor： Alexander Reznicek ,  Ruilong Xie ,  Heng Wu ,  Lan Yu

IPC: H01L43/02 ,  H01L43/12 ,  H01L27/22

Abstract: A memory structure, and a method for forming the same, includes a spin-orbit-torque electrode within a dielectric layer located above a substrate. The spin-orbit-torque electrode including a first conductive material, and a spin-orbit torque via is directly above the spin-orbit-torque electrode that includes a second conductive material. A magnetic tunnel junction pillar is directly above the spin-orbit torque via, and the spin-orbit-torque via contacting a center of a bottom surface of the magnetic-tunnel-junction pillar. A third conductive material is positioned directly below the bottom surface of the magnetic tunnel junction pillar on opposite sides of the spin-orbit torque via and directly above the spin-orbit-torque electrode. The third conductive material, the spin-orbit torque electrode and the spin-orbit torque via form a bottom spin-orbit torque electrode of the magnetic tunnel junction pillar.

公开(公告)号：US20210226034A1

公开(公告)日：2021-07-22

申请号：US16748865

申请日：2020-01-22

Applicant: International Business Machines Corporation

Inventor： Ruilong Xie ,  Lan Yu ,  Heng Wu ,  Kangguo Cheng

IPC: H01L29/66 ,  H01L29/06 ,  H01L29/51

Abstract: Embodiments of the invention are directed to a method of performing fabrication operations to form a nanosheet field effect transistor (FET) device. The fabrication operations include forming a sacrificial structure over a substrate, wherein the sacrificial structure includes a central region, a first leg at a first end of the central region, and a second leg at a second end of the central region. A nanosheet stack is formed over the central region. An isolation material is deposited within a space that was occupied by the sacrificial structure to form a wrap-around bottom dielectric isolation (BDI) structure having a BDI central region, a first BDI leg at a first end of the BDI central region, and a second BDI leg at a second end of the BDI central region.

公开(公告)号：US20210159271A1

公开(公告)日：2021-05-27

申请号：US16695601

申请日：2019-11-26

Applicant: International Business Machines Corporation

Inventor： Alexander Reznicek ,  Ruilong Xie ,  Heng Wu ,  Lan Yu

IPC: H01L27/22 ,  H01L43/12

Abstract: An approach to provide a magnetoresistive random-access memory (MRAM) device that includes a first source/drain contact in a transistor in a semiconductor substrate where the source/drain contact is over a source/drain in the transistor and is surrounded by a first dielectric material. The MRAM device includes a portion of the first source/drain contact connecting to a portion of a bottom electrode of an MRAM device. Furthermore; the MRAM device includes a portion of a top electrode in the MRAM device connecting to a via, wherein the via connects to a M1 metal layer of a semiconductor chip.

公开(公告)号：US11004984B2

公开(公告)日：2021-05-11

申请号：US16578762

申请日：2019-09-23

Applicant: International Business Machines Corporation

Inventor： Heng Wu ,  Oleg Gluschenkov ,  Lan Yu ,  Ruilong Xie

IPC: H01L29/786 ,  H01L29/66 ,  H01L29/78

Abstract: Embodiments of the present invention are directed to forming a nanosheet field effect transistor (FET) having a low resistivity region that reduces the nanosheet external resistance. In a non-limiting embodiment of the invention, a nanosheet stack is formed over a substrate. An inner layer is formed over nanosheets in the nanosheet stack. The inner layer includes a first material having a first melting point. An outer layer is formed over the inner layer. The outer layer includes a second material having a second melting point that is lower than the first melting point. A heavily doped region is formed on a surface of the outer layer and the nanosheet stack is annealed at a temperature between the first melting point and the second melting point such that the outer layer is selectively liquified, distributing the dopants throughout the outer layer.

公开(公告)号：US10971399B2

公开(公告)日：2021-04-06

申请号：US16252763

申请日：2019-01-21

Applicant: International Business Machines Corporation

Inventor： Heng Wu ,  Dechao Guo ,  Junli Wang ,  Ruqiang Bao

IPC: H01L21/768 ,  H01L27/092 ,  H01L23/535 ,  H01L23/532 ,  H01L21/8238 ,  H01L29/66

Abstract: Embodiments of the invention are directed to a method of forming an interconnect structure. A non-limiting example of the method includes forming a transistor over a substrate, forming a dielectric region over the transistor and the substrate, and forming a trench positioned in the dielectric region and over a source or drain (S/D) region of the transistor, wherein a sidewall of the trench includes a gate spacer of the transistor. A volume of the trench is increased by removing the gate spacer from the sidewall of the trench. A first liner and a conductive plug are deposited within a bottom portion of the trench.

公开(公告)号：US10957778B2

公开(公告)日：2021-03-23

申请号：US16738296

申请日：2020-01-09

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Kangguo Cheng ,  Peng Xu ,  Choonghyun Lee ,  Heng Wu

IPC: H01L29/49 ,  H01L21/768 ,  H01L29/66 ,  H01L23/522 ,  H01L29/08

Abstract: A method is presented for reducing parasitic capacitance. The method includes forming a source region and a drain region within a substrate, forming spacers in direct contact with sidewalls of a sacrificial layer, depositing an inter-layer dielectric (ILD) over the source and drain regions, replacing the sacrificial layer with a gate structure, removing the ILD, and depositing a sacrificial dielectric layer. The method further includes removing portions of the sacrificial dielectric layer to expose top surfaces of the source and drain regions, depositing a conductive material over the exposed top surfaces of the source and drain regions, and removing remaining portions of the sacrificial dielectric layer to form air gap spacers between the gate structure and the source and drain regions.

公开(公告)号：US10930563B2

公开(公告)日：2021-02-23

申请号：US16735826

申请日：2020-01-07

Applicant: International Business Machines Corporation

Inventor： Kangguo Cheng ,  Juntao Li ,  Heng Wu ,  Peng Xu

IPC: H01L21/822 ,  H01L21/8238 ,  H01L21/84 ,  H01L27/12 ,  H01L27/092 ,  H01L29/08 ,  H01L29/775 ,  B82Y10/00 ,  H01L29/66 ,  H01L29/06

Abstract: A method for fabricating a stacked nanosheet semiconductor device includes forming nanosheet stacks including alternating silicon layers and silicon germanium layers on a substrate. The method includes patterning a gate structure on the nanosheet stacks and forming a source and drain on the stacks. The method further includes growing a first epitaxial layer on the source and drain. The method includes etching an interlayer dielectric on the first epitaxial layer. The method includes etching a portion of the first epitaxial layer forming a channel and growing a second epitaxial layer and etching a portion of the interlayer etching a portion of the first liner, forming a pFET. The method includes forming an nFET. The method includes the pFET and the nFET being disposed adjacent to one another vertically and a drain of the pFET and a drain of the nFET being electrically connected.

公开(公告)号：US20210013108A1

公开(公告)日：2021-01-14

申请号：US16506339

申请日：2019-07-09

Applicant: International Business Machines Corporation

Inventor： Heng Wu ,  Su Chen Fan ,  Ruilong Xie ,  Huai Huang

IPC: H01L21/8238 ,  H01L27/092 ,  H01L29/08 ,  H01L29/45 ,  H01L29/78 ,  H01L21/285 ,  H01L21/265 ,  H01L21/324 ,  H01L29/66

Abstract: A method for manufacturing a semiconductor device includes forming a first vertical transistor structure in a first device region on a substrate, and forming a second vertical transistor structure in a second device region on the substrate. The first vertical transistor structure includes a first plurality of fins, and the second vertical transistor structure includes a second plurality of fins. A plurality of first source/drain regions are grown from upper portions of the first plurality of fins, and a contact liner layer is formed on the first source/drain regions. The method further includes forming a plurality of first silicide portions from the contact liner layer on the first source/drain regions, and forming a plurality of second silicide portions on a plurality of second source/drain regions extending from upper portions of the second plurality of fins. The second silicide portions have a different composition than the first silicide portions.