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81.发明申请公开(公告)号：US20190252010A1
公开(公告)日：2019-08-15
申请号：US16397154
申请日：2019-04-29
Applicant: International Business Machines Corporation
Inventor： Steven R. Carlough , Susan M. Eickhoff , Warren E. Maule , Patrick J. Meaney , Stephen J. Powell , Gary A. Van Huben , Jie Zheng
CPC classification number: G11C7/109 , G06F3/0611 , G06F3/0626 , G06F3/0658 , G06F3/0659 , G06F3/0685 , G06F12/08 , G11C5/04 , G11C7/1003 , G11C7/1078 , G11C7/22 , G11C2207/2245
Abstract: One or more memory systems, architectural structures, and/or methods of storing information in memory devices is disclosed to improve the data bandwidth and or to reduce the load on the communication links. The system may include one or more memory devices, one or more memory control circuits and one or more data buffer circuits. The memory system, architectural structure and/or method improves the ability of the communications links to transfer data downstream to the data buffer circuits. In one aspect, the memory control circuit receives a store command and a store data tag (Host tag) from a Host and sends the store data command and the store data tag to the data buffer circuits. No store data tag or control signal is sent over the communication links between the Host and the data buffer circuits, only data is sent over the communication links between the Host and the data buffer circuits.
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公开(公告)号：US10353669B2
公开(公告)日：2019-07-16
申请号：US15255543
申请日：2016-09-02
Applicant: International Business Machines Corporation
Inventor： John S. Dodson , Marc A. Gollub , Warren E. Maule , Brad W. Michael
Abstract: Managing entries in a mark table of computer memory errors including identifying at least two mark table entries as candidates for merger, wherein each mark table entry indicates an error at a location in a computer memory; and merging the identified mark table entries into a single mark table entry, including removing one of the identified mark table entries from the mark table.
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公开(公告)号：US09917601B2
公开(公告)日：2018-03-13
申请号：US15226160
申请日：2016-08-02
Applicant: International Business Machines Corporation
Inventor： John K. DeBrosse , Hillery C. Hunter , Charles A. Kilmer , Kyu-hyoun Kim , Warren E. Maule , Rona Yaari
CPC classification number: H03M13/353 , G06F11/1008 , G06F11/1048 , G06F11/1068 , G11C11/4076 , G11C29/52 , G11C2029/0411 , H03M13/09
Abstract: According to one aspect, a method for adaptive error correction in a memory system includes reading data from a memory array of a non-volatile memory device in the memory system. Error correcting logic checks the data for at least one error condition stored in the memory array. Based on determining that the at least one error condition exists, a write-back indicator is asserted by the error correcting logic to request correction of the at least one error condition, where the write-back indicator is a discrete signal sent to a memory controller, and the at least one non-volatile memory device asserting the write-back indicator extends cycle timing monitored by the memory controller while the write-back indicator is asserted. Based on determining that the at least one error condition does not exist, accesses of the memory array continue without asserting the write-back indicator.
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公开(公告)号：US09904611B1
公开(公告)日：2018-02-27
申请号：US15363163
申请日：2016-11-29
Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION
Inventor： Kyu-Hyoun Kim , Warren E. Maule , Kevin M. Mcilvain , Saravanan Sethuraman
CPC classification number: G06F11/2094 , G06F2201/805
Abstract: Examples of techniques for implementing a spare data buffer in a memory are disclosed. In one example implementation according to aspects of the present disclosure, a computer-implemented method may include detecting, by a processor, a failed data buffer in a memory. The method may also include enabling, by the processor, the spare data buffer in the memory. The method may further include extending, by the processor, a buffer communication to the spare data buffer to enable the spare buffer to functionally replace the failed data buffer.
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公开(公告)号：US20170269979A1
公开(公告)日：2017-09-21
申请号：US15070273
申请日：2016-03-15
Applicant: International Business Machines Corporation
Inventor： Marc A. Gollub , Warren E. Maule , Tony E. Sawan , Diyanesh B. Chinnakkonda Vidyapoornachary
IPC: G06F11/07
CPC classification number: G06F11/076 , G06F11/0727 , G06F11/073 , G06F11/106
Abstract: An aspect includes a method for dynamic random access memory (DRAM) scrub and error counting. A scrub operation is performed at memory locations in a DRAM. The performing includes, for each of the memory locations: receiving a refresh command at the DRAM; executing a read/modify/write (RMW) operation at the memory location, the executing including writing corrected bits to the memory location; and incrementing an error count in response to detecting an error during the executing. The method also includes comparing the error count to an error threshold. An alert is initiated in response to the error count exceeding the error threshold.
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Patent Agency Ranking
公开(公告)号：US09760504B2
公开(公告)日：2017-09-12
申请号：US14868558
申请日：2015-09-29
Applicant: International Business Machines Corporation
Inventor： Diyanesh B. Chinnakkonda Vidyapoornachary , Stephen P. Glancy , Hillery C. Hunter , Charles A. Kilmer , Kyu-hyoun Kim , Warren E. Maule , Vipin Patel
CPC classification number: G06F12/1466 , G06F3/0622 , G06F3/0637 , G06F3/0673 , G06F12/0246 , G06F21/88 , G06F2212/1052 , G06F2212/7209
Abstract: Keys are generated at a memory device with a period of time elapsing between generation of each key. A request is received from a memory controller for the most recently generated key. The memory device communicates the first key to the memory controller. Access to nonvolatile memory on the memory device is locked. An unlock command with a second key is received from the memory controller. The memory device determines that the second key matches the first key and unlocks access to the nonvolatile memory in response.
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公开(公告)号：US20170123882A1
公开(公告)日：2017-05-04
申请号：US15401744
申请日：2017-01-09
Applicant: International Business Machines Corporation
Inventor： Michael B. Healy , Hillery C. Hunter , Charles A. Kilmer , Kyu-hyoun Kim , Warren E. Maule
CPC classification number: G06F11/1044 , G06F3/0619 , G06F3/064 , G06F3/0653 , G06F3/0673 , G06F11/0727 , G06F11/076 , G06F11/0766 , G06F11/0772 , G06F11/0793 , G06F11/1008 , G06F11/1024 , G06F11/1048 , H03M13/1515 , H03M13/19
Abstract: Embodiments of the present disclosure provide an approach for monitoring the health and predicting the failure of dynamic random-access memory (DRAM) devices with embedded error-correcting code (ECC). Additional registers are embedded on the DRAM device to store information about the DRAM, such as the number and location of soft errors detected by the device. When the DRAM device detects a soft error, it will update the information stored in the additional registers. A controller compares the information stored in the additional registers to associated thresholds. In some embodiments, after comparing the information to the associated thresholds, the controller may determine whether to schedule a repair action. In other embodiments, the controller may determine whether to alert the memory controller that the DRAM may be failing.
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公开(公告)号：US20170060782A1
公开(公告)日：2017-03-02
申请号：US14868558
申请日：2015-09-29
Applicant: International Business Machines Corporation
Inventor： Diyanesh B. Chinnakkonda Vidyapoornachary , Stephen P. Glancy , Hillery C. Hunter , Charles A. Kilmer , Kyu-hyoun Kim , Warren E. Maule , Vipin Patel
CPC classification number: G06F12/1466 , G06F3/0622 , G06F3/0637 , G06F3/0673 , G06F12/0246 , G06F21/88 , G06F2212/1052 , G06F2212/7209
Abstract: Keys are generated at a memory device with a period of time elapsing between generation of each key. A request is received from a memory controller for the most recently generated key. The memory device communicates the first key to the memory controller. Access to nonvolatile memory on the memory device is locked. An unlock command with a second key is received from the memory controller. The memory device determines that the second key matches the first key and unlocks access to the nonvolatile memory in response.
Abstract translation: 密钥在存储设备中生成，在每个密钥的生成之间经过一段时间。 从存储器控制器接收最近生成的密钥的请求。 存储器件将第一个键传送到存储器控制器。 访问存储设备上的非易失性存储器被锁定。 从存储器控制器接收具有第二密钥的解锁命令。 存储器件确定第二个键匹配第一个键并解锁对非易失性存储器的访问。
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公开(公告)号：US09558850B1
公开(公告)日：2017-01-31
申请号：US14955183
申请日：2015-12-01
Applicant: International Business Machines Corporation
Inventor： John S. Bialas, Jr. , David D. Cadigan , Stephen P. Glancy , Warren E. Maule , Gary A. Van Huben
IPC: G11C29/50 , G11C11/401 , G11C11/4076
CPC classification number: G11C7/22 , G11C7/10 , G11C7/1066 , G11C7/1093 , G11C11/401 , G11C11/4076 , G11C11/409 , G11C11/4093 , G11C29/50012 , G11C2029/5004 , G11C2207/2254
Abstract: A system and method for efficient data eye training reduces the time and resources spent calibrating one or more memory devices. A temporal calibration mechanism reduces the time and resources for calibration by reducing the number tests needed to sufficiently determine the boundaries of the data eye of the memory device. For one or more values of the voltage reference, the temporal calibration mechanism performs a minimal number of tests to find the edges of the data eye for the hold and setup times.
Abstract translation: 用于高效数据眼睛训练的系统和方法减少了用于校准一个或多个存储器设备的时间和资源。 时间校准机制通过减少充分确定存储器件的数据眼的边界所需的数量测试来减少用于校准的时间和资源。 对于电压参考的一个或多个值，时间校准机制执行最少数量的测试以找到保持和建立时间的数据眼的边缘。
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公开(公告)号：US20160342473A1
公开(公告)日：2016-11-24
申请号：US14835804
申请日：2015-08-26
Applicant: International Business Machines Corporation
Inventor： Michael B. Healy , Hillery C. Hunter , Charles A. Kilmer , Kyu-hyoun Kim , Warren E. Maule , Adam J. McPadden
CPC classification number: H03M13/618 , G06F11/1016
Abstract: A memory management system and a method of managing a memory device are described. The system includes a memory device with a memory array to store data and associated error correction coding (ECC) bits and an extended correction table. The extended correction table stores error information additional to the ECC bits for one or more of the data in the memory array. The system also includes a controller to control the memory device to write and read the data.
Abstract translation: 描述了存储器管理系统和管理存储器件的方法。 该系统包括具有存储器阵列以存储数据和相关联的纠错编码（ECC）位和扩展校正表的存储器件。 扩展校正表存储对存储器阵列中的一个或多个数据的ECC位附加的误差信息。 该系统还包括控制器来控制存储器件以写入和读取数据。
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