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    Wavelength locker integrated with a silicon photonics system
    81.
    发明授权
    Wavelength locker integrated with a silicon photonics system 有权

    公开(公告)号：US10164405B2

    公开(公告)日：2018-12-25

    申请号：US16039568

    申请日：2018-07-19

    Applicant: INPHI CORPORATION

    Inventor： Brian Taylor ,  Radhakrishnan L. Nagarajan ,  Masaki Kato

    IPC: H01S5/0687 ,  H04J14/02 ,  H04B10/50 ,  G02B6/125 ,  H01S5/12 ,  G02B6/28 ,  G02B6/42 ,  G02B6/12

    Abstract: A wavelength locker integrated with a silicon photonics transmission system comprising a silicon-on-insulator (SOI) substrate and an input via a power tap coupler to receive a fraction of a transmission signal with one or more frequencies from a primary output path of the silicon photonics transmission system. The wavelength locker further includes a splitter configured to split the input to a first signal in a first path and a second signal in a second path and a first delay-line-interferometer (DLI) coupled to the second path to receive the second signal and configured to generate an interference spectrum and output at least two sub-spectrums tunable to keep quadrature points of the sub-spectrums at respective one or more target frequencies. The wavelength locker is configured to generate an error signal fed back to the silicon photonics transmission system for locking the one or more frequencies at the one or more target frequencies.

    Off quadrature Mach-Zehnder modulator biasing
    82.
    发明授权
    Off quadrature Mach-Zehnder modulator biasing 有权

    公开(公告)号：US10116391B2

    公开(公告)日：2018-10-30

    申请号：US15802338

    申请日：2017-11-02

    Applicant: INPHI CORPORATION

    Inventor： Todd Rope ,  Radhakrishnan L. Nagarajan ,  Hari Shankar

    IPC: G02F1/01 ,  H04B10/516

    Abstract: The present invention relates to telecommunication techniques and integrated circuit (IC) devices. More specifically, embodiments of the present invention provide an off-quadrature modulation system. Once an off-quadrature modulation position is determined, a ratio between DC power transfer amplitude and dither tone amplitude for a modulator is as a control loop target to stabilize off-quadrature modulation. DC power transfer amplitude is obtained by measuring and sampling the output of an optical modulator. Dither tone amplitude is obtained by measuring and sampling the modulator output and performing calculation using the optical modulator output values and corresponding dither tone values. There are other embodiments as well.

    Temperature insensitive delay line interferometer
    83.
    发明授权
    Temperature insensitive delay line interferometer 有权

    公开(公告)号：US09929814B2

    公开(公告)日：2018-03-27

    申请号：US15148710

    申请日：2016-05-06

    Applicant: INPHI CORPORATION

    Inventor： Masaki Kato ,  Radhakrishnan L. Nagarajan

    IPC: H04B10/2507 ,  H04B10/67 ,  H04J14/02 ,  H04B10/69

    CPC classification number: H04B10/677 ,  G02B6/12007 ,  G02B6/12028 ,  G02B6/2813 ,  G02B6/29344 ,  G02B6/29352 ,  H04B10/69 ,  H04J14/02

    Abstract: A silicon photonics based temperature-insensitive delay line interferometer (DLI). The DLI includes a first arm comprising a first length of a first material characterized by a first group index corresponding to a first phase delay to transfer a first light wave with a first peak frequency and a second arm comprising a second length of a second material characterized by a second group index corresponding to a second phase to transfer a second light wave with a second peak frequency with a time-delay difference relative to the first light wave. The first phase delay and the second phase delay are configured to change equally upon a change of temperature. The time-delay difference between the first light wave and the second light wave is set to be inversed value of a free spectral range (FSR) to align at least the first peak frequency to a channel of a designated frequency grid.

    Vertical integration of hybrid waveguide with controlled interlayer thickness
    85.
    发明授权
    Vertical integration of hybrid waveguide with controlled interlayer thickness 有权

    公开(公告)号：US09885831B2

    公开(公告)日：2018-02-06

    申请号：US15586179

    申请日：2017-05-03

    Applicant: INPHI CORPORATION

    Inventor： Liang Ding ,  Radhakrishnan L. Nagarajan

    IPC: H01L21/76 ,  G02B6/132 ,  G02B6/125 ,  G02B6/136 ,  G02B6/12

    CPC classification number: G02B6/132 ,  G02B6/122 ,  G02B6/125 ,  G02B6/136 ,  G02B2006/12061

    Abstract: An silicon photonics device of hybrid waveguides having a coupling interlayer with an accurately controlled thickness and a method of making the same. The device includes a first plurality of Si waveguides formed in a SOI substrate and a first layer of SiO2 overlying the first plurality of Si waveguides and a second plurality of Si3N4 waveguides formed on the first layer of SiO2. At least one Si3N4 waveguide is disposed partially overlapping with at least one of the first plurality Si waveguides in vertical direction separated by the first layer of SiO2 with a thickness controlled no greater than 90 nm. The device includes a second layer of SiO2 overlying the second plurality of Si3N4 waveguides. The method of accurately controlling the coupling interlayer SiO2 thickness includes a multilayer SiO2/Si3N4/SiO2 hard mask process for SiO2 etching and polishing as stopping and buffering layer as well as Si waveguide etching mask.

    Fiber coupler for silicon photonics
    87.
    发明授权
    Fiber coupler for silicon photonics 有权

    公开(公告)号：US09823420B2

    公开(公告)日：2017-11-21

    申请号：US15374977

    申请日：2016-12-09

    Applicant: INPHI CORPORATION

    Inventor： Masaki Kato ,  Radhakrishnan L. Nagarajan

    IPC: G02B6/30 ,  G02B6/122 ,  G02B6/136 ,  G02B6/12

    CPC classification number: G02B6/305 ,  G02B6/1228 ,  G02B6/136 ,  G02B6/26 ,  G02B2006/12061

    Abstract: An apparatus for converting fiber mode to waveguide mode. The apparatus includes a silicon substrate member and a dielectric member having an elongated body. Part of the elongated body from a back end overlies the silicon substrate member and remaining part of the elongated body up to a front end is separated from the silicon substrate member by a second dielectric material at an under region. The apparatus also includes a waveguide including a segment from the back end to a tail end formed on the dielectric member at least partially overlying the remaining part of the elongated body. The segment is buried in a cladding overlying entirely the dielectric member. The cladding has a refractive index that is less than the waveguide but includes an index-graded section with decreasing index that is formed at least over the segment from the tail end toward the back end.

    Built-in self test for loopback on communication system on chip
    88.
    发明授权
    Built-in self test for loopback on communication system on chip 有权

    公开(公告)号：US09774391B2

    公开(公告)日：2017-09-26

    申请号：US15406230

    申请日：2017-01-13

    Applicant: INPHI CORPORATION

    Inventor： Radhakrishnan L. Nagarajan

    IPC: H04B10/071 ,  H04L12/26 ,  H04L12/933 ,  H04Q11/00 ,  H04B10/40

    CPC classification number: H04B10/071 ,  H04B10/40 ,  H04L43/50 ,  H04L49/109 ,  H04Q11/0005 ,  H04Q2011/0018 ,  H04Q2011/0035

    Abstract: In an example, the present invention includes an integrated system-on-chip device. The device is configured on a single silicon substrate member. The device has a data input/output interface provided on the substrate member. The device has an input/output block provided on the substrate member and coupled to the data input/output interface. The device has a signal processing block provided on the substrate member and coupled to the input/output block. The device has a driver module provided on the substrate member and coupled to the signal processing block. In an example, the device has a driver interface provided on the substrate member and coupled to the driver module and configured to be coupled to a silicon photonics device. In an example, a control block is configured to receive and send instruction(s) in a digital format to the communication block and is configured to receive and send signals in an analog format to communicate with the silicon photonics device.

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