公开(公告)号：US20080157261A1

公开(公告)日：2008-07-03

申请号：US12049258

申请日：2008-03-14

申请人： Roger Allen Booth, ,  Louis Lu-Chen Hsu ,  Jack A. Mandelman ,  William R. Tonti

发明人： Roger Allen Booth, ,  Louis Lu-Chen Hsu ,  Jack A. Mandelman ,  William R. Tonti

IPC分类号： H01L27/12

CPC分类号： H01L21/76243

摘要： In an aspect, a method is provided for forming a silicon-on-insulator (SOI) layer. The method includes the steps of (1) providing a silicon substrate; (2) selectively implanting the silicon substrate with oxygen using a low implant energy to form an ultra-thin patterned seed layer; and (3) employing the ultra-thin patterned seed layer to form a patterned SOI layer on the silicon substrate. Numerous other aspects are provided.

摘要翻译： 在一方面，提供了一种用于形成绝缘体上硅（SOI）层的方法。 该方法包括以下步骤：（1）提供硅衬底; （2）使用低注入能量用氧选择性地注入硅衬底以形成超薄图案种子层; 和（3）使用超薄图案种子层在硅衬底上形成图案化SOI层。 提供了许多其他方面。

公开(公告)号：US07388259B2

公开(公告)日：2008-06-17

申请号：US10536483

申请日：2002-11-25

申请人： Bruce B. Doris ,  Dureseti Chidambarrao ,  MeiKei Ieong ,  Jack A. Mandelman

发明人： Bruce B. Doris ,  Dureseti Chidambarrao ,  MeiKei Ieong ,  Jack A. Mandelman

IPC分类号： H01L29/94

CPC分类号： H01L27/1203 ,  H01L21/84 ,  H01L29/7843 ,  H01L29/785

摘要： A semiconductor device structure, includes a PMOS device 200 and an NMOS device 300 disposed on a substrate 1,2, the PMOS device including a compressive layer 6 stressing an active region of the PMOS device, the NMOS device including a tensile layer 9 stressing an active region of the NMOS device, wherein the compressive layer includes a first dielectric material, the tensile layer includes a second dielectric material, and the PMOS and NMOS devices are FinFET devices 200, 300.

摘要翻译： 半导体器件结构包括PMOS器件200和设置在衬底1,2上的NMOS器件300，PMOS器件包括压迫PMOS器件的有源区的压缩层6，NMOS器件包括拉伸层9， 所述NMOS器件的有源区，其中所述压缩层包括第一介电材料，所述拉伸层包括第二介电材料，并且所述PMOS和NMOS器件为FinFET器件200,300。

公开(公告)号：US07358823B2

公开(公告)日：2008-04-15

申请号：US11353516

申请日：2006-02-14

申请人： Wagdi W. Abadeer ,  Anthony R. Bonaccio ,  Jack A. Mandelman ,  William R. Tonti ,  Sebastian T. Ventrone

发明人： Wagdi W. Abadeer ,  Anthony R. Bonaccio ,  Jack A. Mandelman ,  William R. Tonti ,  Sebastian T. Ventrone

IPC分类号： H03B5/12

CPC分类号： H03L7/099 ,  H03B5/1212 ,  H03B5/1228 ,  H03B5/124 ,  H03L7/095 ,  H03L7/10 ,  H03L7/18 ,  H03L2207/06

摘要： In a first aspect, a first method of adjusting capacitance of a semiconductor device is provided. The first method includes the steps of (1) providing a transistor including a dielectric material having a dielectric constant of about 3.9 to about 25, wherein the transistor is adapted to operate in a first mode to provide a capacitance and further adapted to operate in a second mode to change a threshold voltage of the transistor from an original threshold voltage to a changed threshold voltage such that the changed threshold voltage affects a capacitance provided by the transistor when operated in the first mode; and (2) employing the transistor in a circuit. Numerous other aspects are provided.

摘要翻译： 在第一方面，提供了一种调整半导体器件的电容的方法。 第一种方法包括以下步骤：（1）提供包括具有约3.9至约25的介电常数的介电材料的晶体管，其中该晶体管适于在第一模式下工作以提供电容，并进一步适于在 将晶体管的阈值电压从初始阈值电压改变到改变的阈值电压，使得当在第一模式中操作时，改变的阈值电压影响由晶体管提供的电容; 和（2）在电路中采用晶体管。 提供了许多其他方面。

公开(公告)号：US07227233B2

公开(公告)日：2007-06-05

申请号：US11162472

申请日：2005-09-12

申请人： Toshiharu Furukawa ,  Mark C. Hakey ,  Steven J. Holmes ,  David V. Horak ,  Charles W. Koburger, III ,  Jack A. Mandelman

发明人： Toshiharu Furukawa ,  Mark C. Hakey ,  Steven J. Holmes ,  David V. Horak ,  Charles W. Koburger, III ,  Jack A. Mandelman

IPC分类号： H01L29/76 ,  H01L29/94 ,  H01L31/00

CPC分类号： H01L27/1203 ,  H01L27/1021 ,  H01L27/112 ,  H01L27/11213

摘要： A silicon-on-insulator (SOI) Read Only Memory (ROM), and a method of making the SOI ROM. ROM cells are located at the intersections of stripes in the surface SOI layer with orthogonally oriented wires on a conductor layer. Contacts from the wires connect to ROM cell diodes in the upper surface of the stripes. ROM cell personalization is the presence or absence of a diode and/or contact.

摘要翻译： 绝缘体上硅（SOI）只读存储器（ROM）以及制造SOI ROM的方法。 ROM单元位于导体层上的表面SOI层中的条纹与正交取向的导线之间的交叉处。 电线的触点连接到条纹上表面的ROM单元二极管。 ROM单元个性化是存在或不存在二极管和/或接触。

公开(公告)号：US07023041B2

公开(公告)日：2006-04-04

申请号：US10341187

申请日：2003-01-13

申请人： Giuseppe La Rosa ,  Thomas W. Dyer ,  Oleg Gluschenkov ,  Jack A. Mandelman ,  Carl J. Radens ,  Alvin W. Strong

发明人： Giuseppe La Rosa ,  Thomas W. Dyer ,  Oleg Gluschenkov ,  Jack A. Mandelman ,  Carl J. Radens ,  Alvin W. Strong

IPC分类号： H01L27/108 ,  H01L29/76

CPC分类号： H01L29/945 ,  H01L27/10861 ,  H01L27/10894 ,  H01L29/66181

摘要： A versatile structure is formed, based on a deep trench, vertical transistor DRAM cell, that forms a conductive extension of the trench electrode in an elongated trench that contacts the lower electrode of the vertical transistor. The structure can be used as a capacitor, as a discrete transistor as a single-transistor amplifier or as a building block for more complex circuits.

摘要翻译： 基于深沟槽垂直晶体管DRAM单元形成通用结构，其在与垂直晶体管的下电极接触的细长沟槽中形成沟槽电极的导电延伸。 该结构可以用作电容器，作为单晶体管放大器的分立晶体管或作为更复杂电路的构建块。

公开(公告)号：US06884667B1

公开(公告)日：2005-04-26

申请号：US10669727

申请日：2003-09-25

申请人： Bruce B. Doris ,  Dureseti Chidambarrao ,  Xavier Baie ,  Jack A. Mandelman ,  Devendra K. Sadana ,  Dominic J. Schepis

发明人： Bruce B. Doris ,  Dureseti Chidambarrao ,  Xavier Baie ,  Jack A. Mandelman ,  Devendra K. Sadana ,  Dominic J. Schepis

IPC分类号： H01L27/08 ,  H01L21/336 ,  H01L21/8238 ,  H01L21/84 ,  H01L27/092 ,  H01L27/12 ,  H01L29/78 ,  H01L29/786 ,  H01L21/00

CPC分类号： H01L21/84 ,  H01L27/1203 ,  H01L29/66772 ,  H01L29/7842 ,  H01L29/78603 ,  H01L29/78696

摘要： Field effect transistor with increased charge carrier mobility due to stress in the current channel 22. The stress is in the direction of current flow (longitudinal). In PFET device, the stress is compressive; in NFET devices, the stress is tensile. The stress is created by a compressive film 34 in an area 32 under the channel. The compressive film pushes up on the channel 22, causing it to bend. In PFET devices, the compressive film is disposed under ends 31 of the channel (e.g. under the source and drain), thereby causing compression in an upper portion 22A of the channel. In NFET devices, the compressive film is disposed under a middle portion 40 of the channel (e.g. under the gate), thereby causing tension in the, upper portion of the channel. Therefore, both NFET and PFET device can be enhanced. A method for making the devices is included.

摘要翻译： 场效应晶体管由于电流通道22中的应力而具有增加的电荷载流子迁移率。 应力在电流方向（纵向）。 在PFET器件中，应力是压缩的; 在NFET器件中，应力为拉伸。 应力由通道下的区域32中的压缩膜34产生。 压缩膜在通道22上向上推动，使其弯曲。 在PFET器件中，压缩膜设置在通道的端部31（例如在源极和漏极之下），从而在通道的上部22A中引起压缩。 在NFET器件中，压缩膜设置在通道的中间部分40（例如在栅极下），从而在通道的上部产生张力。 因此，可以增强NFET和PFET器件。 包括制造装置的方法。

公开(公告)号：US06734056B2

公开(公告)日：2004-05-11

申请号：US10341831

申请日：2003-01-14

申请人： Jack A. Mandelman ,  Dureseti Chidambarrao

发明人： Jack A. Mandelman ,  Dureseti Chidambarrao

IPC分类号： H01L218238

CPC分类号： H01L27/10864 ,  H01L27/10841 ,  H01L27/10876 ,  H01L27/10885 ,  H01L27/10891

摘要： A 6F2 memory cell structure and a method of fabricating the same. The memory cell structure includes a plurality of memory cells located in a Si-containing substrate which are arranged in rows and columns. Each memory cell includes a double-gated vertical MOSFET having exposed gate conductor regions and two gates formed on opposing sidewalls of the MOSFETs. The memory cell structure also includes a plurality of wordlines overlaying the double-gated vertical MOSFETs and in contact with the exposed gate conductor regions, and a plurality of bitlines that are orthogonal to the wordlines. Trench isolation regions are located adjacent to the rows of memory cells. The memory cell structure also includes a plurality of punch through stop regions located in the Si-containing substrate and self-aligned to the wordlines and bitlines. A portion of the punch through stop regions overlap each other under the bitlines and each region serves to electrically isolate adjacent buried-strap regions from each other.

摘要翻译： 6F 2存储单元结构及其制造方法。 存储单元结构包括位于含Si衬底中的以行和列排列的多个存储单元。 每个存储单元包括具有暴露的栅极导体区域和形成在MOSFET的相对侧壁上的两个栅极的双门控垂直MOSFET。 存储单元结构还包括覆盖双门控垂直MOSFET并与暴露的栅极导体区域接触的多个字线以及与字线正交的多个位线。 沟槽隔离区位于与存储单元行相邻的位置。 存储单元结构还包括位于含硅衬底中并与字线和位线自对准的多个穿通停止区域。 穿通停止区域的一部分在位线之下彼此重叠，并且每个区域用于将相邻的掩埋区域彼此电隔离。

公开(公告)号：US06707095B1

公开(公告)日：2004-03-16

申请号：US10290400

申请日：2002-11-06

申请人： Dureseti Chidambarrao ,  Jack A. Mandelman ,  Carl J. Radens

发明人： Dureseti Chidambarrao ,  Jack A. Mandelman ,  Carl J. Radens

IPC分类号： H01L27108

CPC分类号： H01L27/10876 ,  H01L27/10864 ,  H01L27/10867

摘要： A method is provided for forming a vertical transistor memory cell structure with back-to-back FET cells which are formed in a planar semiconductor substrate with a plurality of deep trenches having vertical FET devices and a plurality of capacitors each located in a separate trench that is formed in the semiconductor substrate. Bilateral outdiffusion strap regions are formed extending into a doped semiconductor well region in the substrate. There are confronting pairs of outdiffusion strap regions extending from adjacent deep benches into the doped well region. An isolation diffusion region is formed in the doped well separating the confronting isolation diffusion regions by extending therebetween.

摘要翻译： 提供了一种用于形成具有背对背FET单元的垂直晶体管存储单元结构的方法，其形成在具有多个具有垂直FET器件的深沟槽的平面半导体衬底中，并且多个电容器分别位于单独的沟槽中， 形成在半导体衬底中。 形成延伸到衬底中的掺杂半导体阱区域中的双边扩散带区域。 存在从相邻的深长板延伸到掺杂阱区域的面向对的向外扩散带区域。 在掺杂阱中形成隔离扩散区，通过在相互隔离扩散区之间延伸来分离相对的隔离扩散区。

公开(公告)号：US06686637B1

公开(公告)日：2004-02-03

申请号：US10301436

申请日：2002-11-21

申请人： Omer Dokumaci ,  Bruce B. Doris ,  Oleg Gluschenkov ,  Jack A. Mandelman ,  Carl Radens

发明人： Omer Dokumaci ,  Bruce B. Doris ,  Oleg Gluschenkov ,  Jack A. Mandelman ,  Carl Radens

IPC分类号： H01L2978

CPC分类号： H01L29/66545 ,  H01L21/26586 ,  H01L21/28035 ,  H01L21/28044 ,  H01L29/1083 ,  H01L29/4925 ,  H01L29/665

摘要： A gate structure for a semiconductor transistor is disclosed. In an exemplary embodiment, the gate structure includes a lower polysilicon region doped at a first dopant concentration and an upper polysilicon region doped at a second concentration, with the second concentration being different than the first concentration. A conductive barrier layer is disposed between the lower and the upper polysilicon regions, wherein the conductive barrier layer prevents diffusion of impurities between the lower and the upper polysilicon regions.

摘要翻译： 公开了一种用于半导体晶体管的栅极结构。 在示例性实施例中，栅极结构包括以第一掺杂剂浓度掺杂的下多晶硅区域和以第二浓度掺杂的上多晶硅区域，其中第二浓度不同于第一浓度。 导电阻挡层设置在下部和上部多晶硅区域之间，其中导电阻挡层防止杂质在下部和上部多晶硅区域之间的扩散。

公开(公告)号：US06646949B1

公开(公告)日：2003-11-11

申请号：US09537498

申请日：2000-03-29

申请人： Wayne F. Ellis ,  Louis L-C. Hsu ,  Jack A. Mandelman ,  William R. Tonti

发明人： Wayne F. Ellis ,  Louis L-C. Hsu ,  Jack A. Mandelman ,  William R. Tonti

IPC分类号： G11C800

CPC分类号： G11C8/08 ,  G11C11/4085

摘要： A word line for a row of memory elements of a dynamic random access memory. A first transistor is connected to a source of negative potential and to the word line for switching the word line to a source of negative potential in response to a decoder signal. A diode is additionally connected to the word line and to a selector signal. A second transistor applies a positive potential to the word line in response to a decoder signal. The word line is charged to a positive potential. The word line is reset to a substantially negative potential in two stages. In the first stage, conduction is through the diode to a ground connection which dissipates a majority of the charge of the word line. The remaining charge is dissipated during a second stage when the first transistor discharges the word line remaining charge through a source of negative potential.

摘要翻译： 用于动态随机存取存储器的一行存储元件的字线。 第一晶体管连接到负电位源和字线，用于响应于解码器信号将字线切换到负电位源。 二极管另外连接到字线和选择器信号。 第二晶体管响应于解码器信号向字线施加正电位。 字线被充电到正电位。 字线在两个阶段重置为基本上为负的电位。 在第一阶段，传导通过二极管到接地连接，消耗字线的大部分电荷。 当第一晶体管通过负电位源将字线剩余电荷放电时，剩余电荷在第二阶段消散。