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44 条记录 (耗时 0.018 秒)

    Word line driver for dynamic random access memories
    3.
    发明授权
    Word line driver for dynamic random access memories 有权
    用于动态随机存取存储器的字线驱动

    公开(公告)号：US06646949B1

    公开(公告)日：2003-11-11

    申请号：US09537498

    申请日：2000-03-29

    申请人： Wayne F. Ellis ,  Louis L-C. Hsu ,  Jack A. Mandelman ,  William R. Tonti

    发明人： Wayne F. Ellis ,  Louis L-C. Hsu ,  Jack A. Mandelman ,  William R. Tonti

    IPC分类号： G11C800

    CPC分类号： G11C8/08 ,  G11C11/4085

    摘要： A word line for a row of memory elements of a dynamic random access memory. A first transistor is connected to a source of negative potential and to the word line for switching the word line to a source of negative potential in response to a decoder signal. A diode is additionally connected to the word line and to a selector signal. A second transistor applies a positive potential to the word line in response to a decoder signal. The word line is charged to a positive potential. The word line is reset to a substantially negative potential in two stages. In the first stage, conduction is through the diode to a ground connection which dissipates a majority of the charge of the word line. The remaining charge is dissipated during a second stage when the first transistor discharges the word line remaining charge through a source of negative potential.

    摘要翻译： 用于动态随机存取存储器的一行存储元件的字线。 第一晶体管连接到负电位源和字线，用于响应于解码器信号将字线切换到负电位源。 二极管另外连接到字线和选择器信号。 第二晶体管响应于解码器信号向字线施加正电位。 字线被充电到正电位。 字线在两个阶段重置为基本上为负的电位。 在第一阶段，传导通过二极管到接地连接，消耗字线的大部分电荷。 当第一晶体管通过负电位源将字线剩余电荷放电时，剩余电荷在第二阶段消散。

    Method of making a high-density DRAM structure on SOI
    6.
    发明授权
    Method of making a high-density DRAM structure on SOI 失效
    在SOI上制造高密度DRAM结构的方法

    公开(公告)号：US5466625A

    公开(公告)日：1995-11-14

    申请号：US346207

    申请日：1994-11-22

    申请人： Chang-Ming Hsieh ,  Louis L. C. Hsu ,  Seiki Ogura

    发明人： Chang-Ming Hsieh ,  Louis L. C. Hsu ,  Seiki Ogura

    IPC分类号： H01L27/04 ,  H01L21/822 ,  H01L21/8242 ,  H01L27/10 ,  H01L27/108

    CPC分类号： H01L27/10829 ,  H01L27/10823

    摘要： A high density, DRAM cell array with a very short channel, vertical gate transfer transistor that can be manufactured using conventional photolithography process steps. The conventional four-by-four DRAM array shown schematically in FIG. 1a is rearranged to the shared-gate, double-bit array shown schematically in FIG. 1b. Trench storage capacitors and vertical FET transistors are arranged in pairs with a common vertical gate and a common substrate, allowing both bit and substrate contacts to be shared by adjacent cells.

    摘要翻译： 具有非常短的通道的高密度DRAM单元阵列，垂直栅极转移晶体管可以使用常规光刻工艺步骤制造。 图1中示意性示出的常规四乘四DRAM阵列。 1a被重新布置到图1中示意性示出的共享门双位阵列。 1b。 沟槽存储电容器和垂直FET晶体管与公共垂直栅极和公共衬底成对配置，允许位和衬底触点由相邻单元共享。

    Vertical gate transistor with low temperature epitaxial channel
    7.
    发明授权
    Vertical gate transistor with low temperature epitaxial channel 失效
    具有低温外延通道的垂直栅极晶体管

    公开(公告)号：US5283456A

    公开(公告)日：1994-02-01

    申请号：US900038

    申请日：1992-06-17

    申请人： Chang-Ming Hsieh ,  Louis L. C. Hsu ,  Seiki Ogura

    发明人： Chang-Ming Hsieh ,  Louis L. C. Hsu ,  Seiki Ogura

    IPC分类号： H01L21/265 ,  H01L21/336 ,  H01L27/12 ,  H01L29/78 ,  H01L29/786 ,  H01L27/01 ,  H01L29/76

    CPC分类号： H01L29/78642 ,  H01L27/1203

    摘要： A field effect transistor (FET) with a vertical gate and a very thin channel sandwiched between source and drain layers. In a preferred embodiment of the invention, the FET is formed on a silicon on insulator (SOI) substrate with the silicon layer serving as the first layer (e.g., the source layer). A low temperature epitaxial (LTE) process is used to form a very thin (e.g., 0.1 .mu.m) channel, and a chemically vapor deposited polysilicon layer forms the top layer (e.g., the drain layer). An opening is etched through the three layers to the insulator substrate and its wall is oxidized, forming a gate oxide. Polysilicon is deposited to fill the opening and form the vertical gate.

    摘要翻译： 具有垂直栅极和夹在源极和漏极层之间的非常薄的沟道的场效应晶体管（FET）。 在本发明的一个优选实施例中，FET在硅绝缘体（SOI）衬底上形成，硅层用作第一层（例如，源层）。 使用低温外延（LTE）工艺来形成非常薄的（例如0.1（m））沟道，并且化学气相沉积的多晶硅层形成顶层（例如，漏层）。 通过三层蚀刻开口到绝缘体衬底，并且其壁被氧化，形成栅极氧化物。 沉积多晶硅以填充开口并形成垂直浇口。