公开(公告)号：US07679409B2

公开(公告)日：2010-03-16

申请号：US12138024

申请日：2008-06-12

Applicant: Mi Hye Kim ,  Jae Jin Lee

Inventor： Mi Hye Kim ,  Jae Jin Lee

IPC: H03B1/00

CPC classification number: H03K19/00323 ,  G11C7/1078 ,  G11C7/1084 ,  H03K19/01721 ,  H03K19/01742 ,  H03K19/018528 ,  H03K19/09429

Abstract: A semiconductor device stabilizes an operation of an input buffer. A semiconductor device includes an input potential detection unit outputting a detection signal in response to a level of an input signal. An input buffer buffers the input signal by performing a differential amplifying operation through a first current sink unit. A second current sink unit, sharing an output with the input buffer, differentially amplifies the input signal of the input buffer in response to a level of the detection signal.

Abstract translation: 半导体器件稳定输入缓冲器的操作。 半导体器件包括输入电位检测单元，其响应于输入信号的电平输出检测信号。 输入缓冲器通过执行通过第一电流吸收器单元的差分放大操作来缓冲输入信号。 与输入缓冲器共享输出的第二电流宿单元响应于检测信号的电平差分地放大输入缓冲器的输入信号。

公开(公告)号：US20100052955A1

公开(公告)日：2010-03-04

申请号：US12474957

申请日：2009-05-29

Applicant: Seung Hyun CHO ,  Moo Kyoung Chung ,  Kyung Su Kim ,  Jae Jin Lee ,  Jun Young Lee ,  Seong Mo Park ,  Nak Woong Eum

Inventor： Seung Hyun CHO ,  Moo Kyoung Chung ,  Kyung Su Kim ,  Jae Jin Lee ,  Jun Young Lee ,  Seong Mo Park ,  Nak Woong Eum

IPC: H03M7/40

CPC classification number: H03M7/425

Abstract: Provided is a table generation method of decoding a variable-length code. The table generation method includes receiving a variable-length code table and a search width N, generating a K-ary tree from the variable-length code table and the search width N, and generating an N-bit code table from the K-ary tree.

Abstract translation: 提供了对可变长度码进行解码的表生成方法。 表生成方法包括从可变长度代码表和搜索宽度N接收可变长度代码表和搜索宽度N，生成K元树，并从K元生成N位代码表 树。

公开(公告)号：US20090282215A1

公开(公告)日：2009-11-12

申请号：US12346803

申请日：2008-12-30

Applicant: Moo Kyoung CHUNG ,  Seong Hyun Cho ,  Kyung Su Kim ,  Jae Jin Lee ,  Jun Young Lee ,  Seong Mo Park ,  Nak Woong Eum

Inventor： Moo Kyoung CHUNG ,  Seong Hyun Cho ,  Kyung Su Kim ,  Jae Jin Lee ,  Jun Young Lee ,  Seong Mo Park ,  Nak Woong Eum

IPC: G06F15/76 ,  G06F9/02

CPC classification number: G06F9/3885 ,  G06F9/38 ,  G06F15/17375

Abstract: Provided are a multi-processor system and a multi-processing method in the multi-processor system. The multi-processor system comprises a plurality of processors each including a data core and a processing core; and switches connecting the data core to the processing core in each of the processors as a combination of a data core-processing core pair. Therefore, the multi-processor system may be useful to remove any overhead for communications and make programming easy and simple.

Abstract translation: 在多处理器系统中提供多处理器系统和多处理方法。 多处理器系统包括多个处理器，每个处理器包括数据核心和处理核心; 并且将数据核心连接到每个处理器中的处理核心，作为数据核心处理核心对的组合。 因此，多处理器系统可能有助于消除通信的任何开销，并使编程变得简单和简单。

公开(公告)号：US07564122B2

公开(公告)日：2009-07-21

申请号：US11365246

申请日：2006-03-01

Applicant: Jae Hak Yee ,  Young Suk Chung ,  Jae Jin Lee ,  Terry Davis ,  Chung Suk Han ,  Jae Hun Ku ,  Jae Sung Kwak ,  Sang Hyun Ryu

Inventor： Jae Hak Yee ,  Young Suk Chung ,  Jae Jin Lee ,  Terry Davis ,  Chung Suk Han ,  Jae Hun Ku ,  Jae Sung Kwak ,  Sang Hyun Ryu

IPC: H01L23/495

CPC classification number: H01L23/3107 ,  H01L23/4951 ,  H01L23/49541 ,  H01L23/49548 ,  H01L23/49551 ,  H01L24/32 ,  H01L24/48 ,  H01L24/73 ,  H01L2224/05599 ,  H01L2224/29007 ,  H01L2224/32014 ,  H01L2224/32245 ,  H01L2224/48091 ,  H01L2224/48247 ,  H01L2224/73265 ,  H01L2224/85399 ,  H01L2924/00014 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01027 ,  H01L2924/01033 ,  H01L2924/01047 ,  H01L2924/0106 ,  H01L2924/01075 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/07802 ,  H01L2924/12042 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2924/00012 ,  H01L2924/3512 ,  H01L2924/00 ,  H01L2224/45015 ,  H01L2924/207 ,  H01L2224/45099

Abstract: A lead frame for making a semiconductor package is disclosed. The leadframe's leads include a lead lock provided at a free end of each inner lead that is adapted to increase a bonding force of the inner lead to a resin encapsulate, thereby effectively preventing a separation of the inner lead from occurring in a singulation process involved in the fabrication of the semiconductor package. A semiconductor package fabricated using the lead frame and a fabrication method for the semiconductor package are also disclosed. The lead frame includes a paddle, a plurality of tie bars for supporting the corners of the paddle, a plurality of leads arranged at each of four sides or two facing sides of the paddle in such a fashion that they are spaced apart from an adjacent side of the paddle while extending perpendicularly to the associated side of the paddle, each of the leads having lead separation preventing means adapted to increase a bonding force of the lead to a resin encapsulate subsequently molded to encapsulate the lead frame for fabrication of the semiconductor package, and dam bars for supporting the leads and the tie bars. Additional package embodiments include exposed protrusions extending downward from the leads. The exposed protrusions are irradiated with a laser to remove set resin prior to a solder ball attachment step.

Abstract translation: 公开了一种用于制造半导体封装的引线框架。 引线框架的引线包括提供在每个内引线的自由端处的引线锁，其适于增加内引线与树脂封装件的结合力，从而有效地防止内引线的分离在所涉及的单个加工过程中发生 制造半导体封装。 还公开了使用引线框制造的半导体封装和用于半导体封装的制造方法。 引线框架包括桨，用于支撑桨的角的多个连杆，多个引线，其布置在桨的四个侧面或两个相对的侧面中，使得它们与相邻侧面间隔开 的叶片，同时垂直于桨叶的相关侧延伸，每个引线具有引线分离防止装置，其适于增加引线与随后模制的树脂封装件的结合力，以封装引线框架以制造半导体封装， 和用于支撑引线和连接条的阻挡条。 另外的封装实施例包括从引线向下延伸的暴露突起。 在焊球附着步骤之前，用激光照射暴露的突起以去除固化树脂。

公开(公告)号：US07468628B2

公开(公告)日：2008-12-23

申请号：US11623396

申请日：2007-01-16

Applicant: Jae Hyuk Im ,  Jae Jin Lee

Inventor： Jae Hyuk Im ,  Jae Jin Lee

IPC: G05F1/00 ,  H03B5/24

CPC classification number: H02M3/073 ,  H02M2001/0041

Abstract: An internal voltage generator capable of reducing the variation width in the level of an internal voltage VPP, by performing charge pumping only a predetermined number of times in a period where an oscillator driving signal is at a logic HIGH level, and then stopping the charge pumping operation. The oscillator controller generates an oscillation control signal for stopping an oscillation operation of a ring oscillator by using an output signal of a level detector and an output signal of the ring oscillator. The ring oscillator does not generate an oscillation signal at a predetermined time point where an output signal of the level detector is at a HIGH level in response to the oscillation control signal. The charge pump circuit generates an internal voltage by performing a charge pumping operation only predetermined times in response to the oscillation signal, and then stopping the charge pumping operation.

Abstract translation: 内部电压发生器能够通过在振荡器驱动信号处于逻辑高电平的时段内仅进行预定次数的电荷泵浦来减小内部电压VPP的电平的变化宽度，然后停止电荷泵送 操作。 振荡器控制器通过使用电平检测器的输出信号和环形振荡器的输出信号产生用于停止环形振荡器的振荡操作的振荡控制信号。 响应于振荡控制信号，在电平检测器的输出信号处于高电平的预定时间点，环形振荡器不产生振荡信号。 电荷泵电路通过响应于振荡信号仅进行预定次数的电荷泵送操作来产生内部电压，然后停止电荷泵送操作。

公开(公告)号：US07274593B2

公开(公告)日：2007-09-25

申请号：US11115302

申请日：2005-04-27

Applicant: Hee Bok Kang ,  Jin Hong Ahn ,  Jae Jin Lee

Inventor： Hee Bok Kang ,  Jin Hong Ahn ,  Jae Jin Lee

IPC: G11C16/04

CPC classification number: G11C11/22 ,  H01L27/11502 ,  H01L27/11585 ,  H01L27/1159 ,  H01L29/6684 ,  H01L29/78391

Abstract: A nonvolatile ferroelectric memory device is provided so as to control read/write operations of a nonvolatile memory cell using a channel resistance of the memory cell which is differentiated by polarity states of a ferroelectric material. In the memory device, an insulating layer is formed on a bottom word line, and a floating channel layer comprising a P-type drain region, a P-type channel region and a P-type source region is formed on the insulating layer. Then, a ferroelectric layer is formed on the floating channel layer, and a word line is formed on the ferroelectric layer. As a result, the resistance state induced to the channel region is controlled depending on the polarity of the ferroelectric layer, thereby regulating the read/write operations of the memory cell array.

Abstract translation: 提供非易失性铁电存储器件，以便使用由铁电材料的极性状态区分的存储单元的沟道电阻来控制非易失性存储单元的读/写操作。 在存储器件中，在底部字线上形成绝缘层，在绝缘层上形成包括P型漏极区域，P型沟道区域和P型源极区域的浮动沟道层。 然后，在浮动沟道层上形成铁电体层，在铁电体层上形成字线。 结果，根据铁电层的极性来控制感应到沟道区的电阻状态，从而调节存储单元阵列的读/写操作。

公开(公告)号：US07057280B2

公开(公告)日：2006-06-06

申请号：US10667227

申请日：2003-09-18

Applicant: Jae Hak Yee ,  Young Suk Chung ,  Jae Jin Lee ,  Terry Davis ,  Chung Suk Han ,  Jae Hun Ku ,  Jae Sung Kwak ,  Sang Hyun Ryu

Inventor： Jae Hak Yee ,  Young Suk Chung ,  Jae Jin Lee ,  Terry Davis ,  Chung Suk Han ,  Jae Hun Ku ,  Jae Sung Kwak ,  Sang Hyun Ryu

IPC: H01L23/04

CPC classification number: H01L23/3107 ,  H01L23/4951 ,  H01L23/49541 ,  H01L23/49548 ,  H01L23/49551 ,  H01L24/32 ,  H01L24/48 ,  H01L24/73 ,  H01L2224/05599 ,  H01L2224/29007 ,  H01L2224/32014 ,  H01L2224/32245 ,  H01L2224/48091 ,  H01L2224/48247 ,  H01L2224/73265 ,  H01L2224/85399 ,  H01L2924/00014 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01027 ,  H01L2924/01033 ,  H01L2924/01047 ,  H01L2924/0106 ,  H01L2924/01075 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/07802 ,  H01L2924/12042 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2924/00012 ,  H01L2924/3512 ,  H01L2924/00 ,  H01L2224/45015 ,  H01L2924/207 ,  H01L2224/45099

Abstract: A lead frame for making a semiconductor package is disclosed. The leadframe's leads include a lead lock provided at a free end of each inner lead that is adapted to increase a bonding force of the inner lead to a resin encapsulate, thereby effectively preventing a separation of the inner lead from occurring in a singulation process involved in the fabrication of the semiconductor package. A semiconductor package fabricated using the lead frame and a fabrication method for the semiconductor package are also disclosed. The lead frame includes a paddle, a plurality of tie bars for supporting the corners of the paddle, a plurality of leads arranged at each of four sides or two facing sides of the paddle in such a fashion that they are spaced apart from an adjacent side of the paddle while extending perpendicularly to the associated side of the paddle, each of the leads having lead separation preventing means adapted to increase a bonding force of the lead to a resin encapsulate subsequently molded to encapsulate the lead frame for fabrication of the semiconductor package, and dam bars for supporting the leads and the tie bars. Additional package embodiments include exposed protrusions extending downward from the leads. The exposed protrusions are irradiated with a laser to remove set resin prior to a solder ball attachment step.

Abstract translation: 公开了一种用于制造半导体封装的引线框架。 引线框架的引线包括提供在每个内引线的自由端处的引线锁，其适于增加内引线与树脂封装件的结合力，从而有效地防止内引线的分离在所涉及的单个加工过程中发生 制造半导体封装。 还公开了使用引线框制造的半导体封装和用于半导体封装的制造方法。 引线框架包括桨，用于支撑桨的角的多个连杆，多个引线，其布置在桨的四个侧面或两个相对的侧面中，使得它们与相邻侧面间隔开 的叶片，同时垂直于桨叶的相关侧延伸，每个引线具有引线分离防止装置，其适于增加引线与随后模制的树脂封装件的结合力，以封装引线框架以制造半导体封装， 和用于支撑引线和连接条的阻挡条。 另外的封装实施例包括从引线向下延伸的暴露突起。 在焊球附着步骤之前，用激光照射暴露的突起以去除固化树脂。

公开(公告)号：US06943708B2

公开(公告)日：2005-09-13

申请号：US10893336

申请日：2004-07-19

Applicant: Sang Woon Suh ,  Jin Yong Kim ,  Jae Jin Lee ,  Joo Hyun Lee

Inventor： Sang Woon Suh ,  Jin Yong Kim ,  Jae Jin Lee ,  Joo Hyun Lee

IPC: H03M7/14 ,  G11B20/14 ,  H03M5/14 ,  H03M7/00 ,  H03M7/46

CPC classification number: H03M7/46 ,  G11B20/1426 ,  G11B2020/1457 ,  H03M5/145

Abstract: A method and apparatus of converting a series of data words into modulated signals generates for each data words, a number of intermediate sequences by combining mutually different digital words with a data word, scrambles the intermediate sequences to form alternative sequences, translates each alternataive sequence into a (d,k) constrained sequences, measures for each (d,k) constrained sequences, not only an inclusion rate of an undesired sub-sequence but also a running DSV (Digital Sum Value), and selects one (d,k) constrained sequence having a small inclusion rate for recording on an optical or magneto-optical recording medium among the (d,k) constrained sequences having maximum value of running DSV, smaller than a preset limit. Accordingly, efficient DSV control can be achieved for even relatively-long sequences.

Abstract translation: 将一系列数据字转换成调制信号的方法和装置通过将相互不同的数字字与数据字相结合，为每个数据字生成多个中间序列，对中间序列进行加扰以形成替代序列，将每个交替序列转换成 （d，k）约束序列，每个（d，k）约束序列的测量，不仅是不期望的子序列的包含率，而且是运行的DSV（数字和值），并且选择一个（d，k） 约束序列具有小的包含率用于在具有最大值的运行DSV的（d，k）约束序列中的光学或磁光记录介质上记录，小于预设极限。 因此，对于甚至相对较长的序列，可以实现有效的DSV控制。

公开(公告)号：US6100753A

公开(公告)日：2000-08-08

申请号：US137886

申请日：1998-08-21

Applicant: Chang Seok Lee ,  Min Gun Kim ,  Jae Jin Lee ,  Kwang Eui Pyun

Inventor： Chang Seok Lee ,  Min Gun Kim ,  Jae Jin Lee ,  Kwang Eui Pyun

IPC: H01L29/70 ,  G05F3/24 ,  G05F1/10

CPC classification number: G05F3/247 ,  G05F3/245

Abstract: The present invention relates to a bias stabilization circuit, specifically to a bias stabilization circuit for minimizing the current variations of amplification transistors caused by variations of device parameters which occur during the manufacturing of high-frequency integrated circuits using field-effect transistors, and caused by variations of supply voltage and temperature. In the present invention, the above problem is solved by configuring a level shifter circuit between the drain node and the gate node of the reference voltage generation transistor. Further, by using a constant current source utilizing a depletion transistor and series feedback resistors as a reference current, this circuit becomes stable against the variations of the device parameters as well as the variations of the temperature and supply voltage.

Abstract translation: 本发明涉及一种偏置稳定电路，特别涉及一种偏置稳定电路，用于使由场效应晶体管制造高频集成电路期间发生的器件参数变化引起的放大晶体管的电流变化最小化，并由 电源电压和温度变化。 在本发明中，通过在基准电压产生晶体管的漏极节点和栅极节点之间配置电平移位电路来解决上述问题。 此外，通过使用利用耗尽晶体管和串联反馈电阻器的恒流源作为参考电流，该电路针对器件参数的变化以及温度和电源电压的变化而变得稳定。

公开(公告)号：US6064619A

公开(公告)日：2000-05-16

申请号：US106308

申请日：1998-06-29

Applicant: Seung Han Ahn ,  Jae Jin Lee

Inventor： Seung Han Ahn ,  Jae Jin Lee

IPC: G11C11/401 ,  G11C7/10 ,  G11C8/12 ,  G11C11/406 ,  G11C11/407 ,  G11C11/41 ,  G11C8/00

CPC classification number: G11C7/1045 ,  G11C8/12

Abstract: This invention relates to a synchronous dynamic random access memory in a semiconductor memory device, and particularly to a SDRAM in which a user can program a two (2) bank option or a four (4) bank option using an external signal so that it is possible to select one or more banks. An input section receives an external signal, an operation mode section stores an output signal from the input section, and a bank transformation section selects one or more banks using an output signal from the operation mode memory section. When adapted to a SDRAM, it is possible to operate a circuit having banks of different number from each other using an identical design.

Abstract translation: 本发明涉及一种半导体存储器件中的同步动态随机存取存储器，特别涉及一种SDRAM，其中用户可以使用外部信号编程二（2）存储体选项或四（4）存储体选项，使得它是 可能选择一个或多个银行。 输入部分接收外部信号，操作模式部分存储来自输入部分的输出信号，并且存储体变换部分使用来自操作模式存储器部分的输出信号来选择一个或多个存储体。 当适用于SDRAM时，可以使用相同的设计来操作具有彼此不同数量的组的电路。