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148 条记录 (耗时 0.029 秒)

    Method of forming a memory cell having self-aligned contact regions
    83.
    发明申请
    Method of forming a memory cell having self-aligned contact regions 有权
    形成具有自对准接触区域的存储单元的方法

    公开(公告)号：US20050218458A1

    公开(公告)日：2005-10-06

    申请号：US11141312

    申请日：2005-06-01

    申请人： Ji-Young Kim ,  Jin-Jun Park

    发明人： Ji-Young Kim ,  Jin-Jun Park

    IPC分类号： H01L21/8234 ,  H01L21/336 ,  H01L21/60 ,  H01L21/8242 ,  H01L27/088 ,  H01L27/108 ,  H01L29/76 ,  H01L29/78

    CPC分类号： H01L27/10855 ,  H01L21/76897 ,  H01L27/0207 ,  H01L27/10829 ,  H01L27/10876 ,  H01L27/10888 ,  H01L27/10891 ,  H01L29/66621 ,  H01L29/7834 ,  H01L2924/3011

    摘要： A memory cell of a semiconductor device and a method for forming the same, wherein the memory cell includes a substrate having active regions and field regions, a gate layer formed over the substrate, the gate layer including a plurality of access gates formed over the active regions of the substrate and a plurality of pass gates formed over the field regions of the substrate, first self-aligned contact regions formed between adjacent pass gates and access gates, and second self-aligned contact regions formed between adjacent access gates, wherein a width of each of the first self-aligned contact regions is larger than a width of each of the second self-aligned contact regions.

    摘要翻译： 半导体器件的存储单元及其形成方法，其中存储单元包括具有有源区和场区的衬底，形成在衬底上的栅极层，栅层包括形成在有源区上的多个存取栅极 衬底的区域和形成在衬底的场区域上的多个通过栅极，形成在相邻栅极和存取栅极之间的第一自对准接触区域和形成在相邻栅极之间的第二自对准接触区域，其中宽度 每个第一自对准接触区域的宽度大于第二自对准接触区域中的每一个的宽度。

    Integration method of a semiconductor device having a recessed gate electrode
    84.
    发明授权
    Integration method of a semiconductor device having a recessed gate electrode 有权
    具有凹陷栅电极的半导体器件的集成方法

    公开(公告)号：US06939765B2

    公开(公告)日：2005-09-06

    申请号：US10649262

    申请日：2003-08-26

    申请人： Ji-Young Kim ,  Hyoung-Sub Kim

    发明人： Ji-Young Kim ,  Hyoung-Sub Kim

    IPC分类号： H01L21/8242 ,  H01L21/336 ,  H01L21/8234 ,  H01L27/108 ,  H01L29/423 ,  H01L29/80

    CPC分类号： H01L21/823456 ,  H01L21/823437 ,  H01L27/10876 ,  H01L27/10891 ,  H01L27/10894 ,  H01L27/10897

    摘要： Embodiments of the invention are directed to an integrated circuit device and a method for forming the device. In some embodiments of the invention, two types of transistors are formed on a single substrate, transistors: transistors having a recessed gate, and transistors having a planer gate electrode. In other embodiments, transistors having a recessed gate are formed in multiple areas of the same substrate. Additionally, gates of the transistors in more than one region may be formed simultaneously.

    摘要翻译： 本发明的实施例涉及集成电路器件和用于形成器件的方法。 在本发明的一些实施例中，在单个衬底上形成两种类型的晶体管，晶体管：具有凹陷栅极的晶体管，以及具有平面栅电极的晶体管。 在其他实施例中，具有凹陷栅极的晶体管形成在相同衬底的多个区域中。 此外，可以同时形成多于一个区域中的晶体管的栅极。

    Recess gate transistor structure for use in semiconductor device and method thereof
    85.
    发明申请
    Recess gate transistor structure for use in semiconductor device and method thereof 有权
    用于半导体器件的栅极晶体管结构及其方法

    公开(公告)号：US20050087776A1

    公开(公告)日：2005-04-28

    申请号：US10968599

    申请日：2004-10-18

    申请人： Ji-Young Kim

    发明人： Ji-Young Kim

    IPC分类号： H01L21/336 ,  H01L29/78 ,  H01L29/80

    CPC分类号： H01L29/66621 ,  H01L29/7834

    摘要： An inner spacer is formed in a sidewall of a gate in contact with a first active region that is electrically connected to an upper capacitor, thereby reducing a gate induced drain leakage (GIDL). A structure of a recess gate transistor includes a gate insulation layer, a gate electrode, a first gate spacer, a second gate spacer and source/drain regions. The gate insulation layer is formed within a recess. The gate electrode is surrounded by the gate insulation layer and is extended from within the recess. The first gate spacer is spaced with a predetermined distance horizontally with a portion of the gate insulation layer, being formed in a sidewall of the gate electrode. The second gate spacer is formed in another part of the sidewall of the gate electrode. The source/drain regions are formed mutually oppositely on first and second active regions with the gate electrode therebetween.

    摘要翻译： 内部间隔件形成在栅极的侧壁中，与与上部电容器电连接的第一有源区域接触，由此减小栅极引起漏极泄漏（GIDL）。 凹槽栅极晶体管的结构包括栅极绝缘层，栅极电极，第一栅极间隔物，第二栅极间隔物和源极/漏极区域。 栅极绝缘层形成在凹部内。 栅电极被栅绝缘层包围，并从凹槽内延伸。 第一栅极间隔物与门极绝缘层的一部分水平地间隔预定距离，形成在栅电极的侧壁中。 第二栅极间隔物形成在栅电极的侧壁的另一部分中。 源极/漏极区域在第一和第二有源区域上彼此相对地形成，栅电极在它们之间。

    Self-aligned inner gate recess channel transistor and method of forming the same
    86.
    发明申请
    Self-aligned inner gate recess channel transistor and method of forming the same 有权
    自对准内门凹槽通道晶体管及其形成方法

    公开(公告)号：US20050020086A1

    公开(公告)日：2005-01-27

    申请号：US10730996

    申请日：2003-12-10

    申请人： Ji-Young Kim ,  Chang-Hyun Cho ,  Soo-Ho Shin ,  Tae-Young Chung

    发明人： Ji-Young Kim ,  Chang-Hyun Cho ,  Soo-Ho Shin ,  Tae-Young Chung

    IPC分类号： H01L21/28 ,  H01L21/336 ,  H01L29/423 ,  H01L29/49 ,  H01L29/78 ,  H01L21/311

    CPC分类号： H01L29/66553 ,  H01L29/4238 ,  H01L29/66621 ,  H01L29/7834

    摘要： A self-aligned inner gate recess channel in a semiconductor substrate includes a recess trench formed in an active region of the substrate, a gate dielectric layer formed on a bottom portion of the recess trench, recess inner sidewall spacers formed on sidewalls of the recess trench, a gate formed in the recess trench so that an upper portion of the gate protrudes above an upper surface of the substrate, wherein a thickness of the recess inner sidewall spacers causes a center portion of the gate to have a smaller width than the protruding upper portion and a lower portion of the gate, a gate mask formed on the gate layer, gate sidewall spacers formed on the protruding upper portion of gate and the gate mask, and a source/drain region formed in the active region of the substrate adjacent the gate sidewall spacers.

    摘要翻译： 半导体衬底中的自对准内门凹槽通道包括形成在衬底的有源区中的凹槽，形成在凹槽的底部的栅介电层，形成在凹槽沟槽的侧壁上的凹陷内侧壁 形成在所述凹槽中的栅极，使得所述栅极的上部突出于所述基板的上表面之上，其中所述凹陷内侧壁间隔物的厚度使得所述栅极的中心部分具有比所述突出的上部 栅极的部分和下部，形成在栅极层上的栅极掩模，形成在栅极的突出上部上的栅极侧壁间隔物和栅极掩模，以及形成在邻近基板的基板的有源区域中的源极/漏极区域 门侧壁间隔件。

    Recess type transistor and method of fabricating the same
    87.
    发明申请
    Recess type transistor and method of fabricating the same 审中-公开
    凹陷型晶体管及其制造方法

    公开(公告)号：US20050001266A1

    公开(公告)日：2005-01-06

    申请号：US10871193

    申请日：2004-06-18

    申请人： Ji-Young Kim

    发明人： Ji-Young Kim

    IPC分类号： H01L21/336 ,  H01L21/8234 ,  H01L21/8238 ,  H01L29/10 ,  H01L29/423 ,  H01L29/78 ,  H01L29/94

    CPC分类号： H01L29/66621 ,  H01L21/823412 ,  H01L21/823437 ,  H01L21/823487 ,  H01L21/823807 ,  H01L21/823828 ,  H01L21/823885 ,  H01L29/1033 ,  H01L29/42376 ,  H01L29/7834

    摘要： Embodiments of the invention include a semiconductor substrate having an active region defined by a device isolation film, at least one trench formed in the active region, and a growth silicon layer formed along an internal face of the trench. The transistor also includes a first impurity region of first conductive type that is formed on a boundary region between the growth silicon layer and its opposite active region, and a gate insulation layer formed on upper parts of the growth silicon layer within the trench and the active region. Embodiments include a gate electrode having an upper part and a lower part, the gate electrode formed on the gate insulation layer, the upper part wider than the lower part, the upper part partially overlapping the growth silicon layer; and a second impurity region of second conductive type formed in the active region at both sides of the gate electrode.

    摘要翻译： 本发明的实施例包括具有由器件隔离膜限定的有源区，在有源区中形成的至少一个沟槽和沿沟槽的内表面形成的生长硅层的半导体衬底。 晶体管还包括第一导电类型的第一杂质区，其形成在生长硅层与其相对的有源区之间的边界区域上，以及形成在沟槽内的生长硅层的上部的栅极绝缘层和活性层 地区。 实施例包括具有上部和下部的栅电极，栅电极形成在栅极绝缘层上，上部比下部更宽，上部与生长硅层部分重叠; 以及形成在栅电极两侧的有源区中的第二导电类型的第二杂质区。

    Organic light emitting display device and manufacturing method thereof
    90.
    发明授权
    Organic light emitting display device and manufacturing method thereof 有权
    有机发光显示装置及其制造方法

    公开(公告)号：US09029857B2

    公开(公告)日：2015-05-12

    申请号：US13096330

    申请日：2011-04-28

    申请人： Jin-Goo Kang ,  Young-In Hwang ,  Ji-Young Kim ,  Hyo-Seok Kim

    发明人： Jin-Goo Kang ,  Young-In Hwang ,  Ji-Young Kim ,  Hyo-Seok Kim

    IPC分类号： H01L27/32

    CPC分类号： H01L27/3223

    摘要： An organic light-emitting display device includes a substrate including a rectangular light-emitting area and a circuit area, the circuit area including a thin film transistor, the light-emitting area including an electroluminescent layer produced by a solution deposition process, the light-emitting area being bounded by a first major side, a second major side, a first minor side and a second minor side, the first major side being opposite from and parallel to a second major side, each of these sides having wiring or dummies arranged thereat, and a pixel defining layer arranged on the wirings and on the dummies. In order to produce a uniform thickness electroluminescent layer via a solution deposition process, top surfaces of the pixel defining layer on each of the wirings and dummies that border the light emitting area are arranged in a same plane that is parallel to the substrate.

    摘要翻译： 有机发光显示装置包括具有矩形发光区域和电路区域的基板，所述电路区域包括薄膜晶体管，所述发光区域包括通过溶液沉积工艺制造的电致发光层， 发光区域由第一主侧面，第二主侧面，第一次侧面和第二次要侧面限定，第一主侧面与第二主侧面相对并平行，其中每个侧面布置有布线或虚拟物 以及布置在布线和虚拟物上的像素限定层。 为了通过溶液沉积工艺制造出均匀的厚度的电致发光层，每个布线上的像素限定层的顶表面和与发光区域相邻的虚拟体被布置在与衬底平行的同一平面中。