公开(公告)号：US20130221447A1

公开(公告)日：2013-08-29

申请号：US13754063

申请日：2013-01-30

申请人： Choong-Ho Lee ,  Donggu Yi ,  Seung Chul Lee ,  Hyungsuk Lee ,  Seonah Nam ,  Changwoo Oh ,  Jongwook Lee ,  Song-Yi Han

发明人： Choong-Ho Lee ,  Donggu Yi ,  Seung Chul Lee ,  Hyungsuk Lee ,  Seonah Nam ,  Changwoo Oh ,  Jongwook Lee ,  Song-Yi Han

IPC分类号： H01L27/092

CPC分类号： H01L29/6681 ,  H01L21/02255 ,  H01L21/32053 ,  H01L21/76224 ,  H01L27/092 ,  H01L29/517 ,  H01L29/66545 ,  H01L29/66795 ,  H01L29/7848 ,  H01L29/785

摘要： Provided are field effect transistors and methods of fabricating the same. The transistor may include a substrate with an active pattern, the active pattern having a top surface and two sidewalls, a gate electrode proximal to the top surface and the sidewalls of the active pattern and crossing the active pattern, a gate spacer covering a sidewall of the gate electrode, a gate dielectric pattern at a bottom surface of the gate electrode, a source electrode on the active pattern at one side of the gate electrode, a drain electrode on the active pattern at another side of the gate electrode, and silicide patterns on surfaces of the source and drain electrodes, respectively. The gate dielectric pattern includes at least one high-k layer and the gate spacer has a dielectric constant that is smaller than that of the gate dielectric pattern.

公开(公告)号：US08455344B2

公开(公告)日：2013-06-04

申请号：US13238084

申请日：2011-09-21

申请人： Suk-Kang Sung ,  Choong-Ho Lee ,  Dong-Uk Choi ,  Hee-Soo Kang

发明人： Suk-Kang Sung ,  Choong-Ho Lee ,  Dong-Uk Choi ,  Hee-Soo Kang

IPC分类号： H01L21/28

CPC分类号： H01L27/11568

摘要： A non-volatile memory device includes field insulating layer patterns on a substrate to define an active region of the substrate, upper portions of the field insulating layer patterns protruding above an upper surface of the substrate, a tunnel insulating layer on the active region, a charge trapping layer on the tunnel insulating layer, a blocking layer on the charge trapping layer, first insulating layers on upper surfaces of the field insulating layer patterns, and a word line structure on the blocking layer and first insulating layers.

摘要翻译： 非易失性存储器件包括在衬底上的场绝缘层图案，以限定衬底的有源区，场绝缘层图案的上部突出在衬底的上表面上，在有源区上的隧道绝缘层， 隧道绝缘层上的电荷俘获层，电荷俘获层上的阻挡层，场绝缘层图案的上表面上的第一绝缘层，以及阻挡层和第一绝缘层上的字线结构。

公开(公告)号：US08422290B2

公开(公告)日：2013-04-16

申请号：US13072022

申请日：2011-03-25

申请人： Hee-Soo Kang ,  Choong-Ho Lee ,  Dong-Uk Choi

发明人： Hee-Soo Kang ,  Choong-Ho Lee ,  Dong-Uk Choi

IPC分类号： G11C16/04

CPC分类号： G11C16/10 ,  G11C16/0483 ,  H01L27/11524

摘要： Methods of programming data in a non-volatile memory cell are provided. A memory cell according to some embodiments may include a gate structure that includes a tunnel oxide layer pattern, a floating gate, a dielectric layer and a control gate sequentially stacked on a substrate, impurity regions that are formed in the substrate at both sides of the gate structure, and a conductive layer pattern that is arranged spaced apart from and facing the floating gate. Embodiments of such methods may include applying a programming voltage to the control gate, grounding the impurity regions and applying a fringe voltage to the conductive layer pattern to generate a fringe field in the floating gate.

摘要翻译： 提供了在非易失性存储单元中编程数据的方法。 根据一些实施例的存储器单元可以包括栅极结构，其包括隧道氧化物层图案，浮动栅极，电介质层和顺序堆叠在衬底上的控制栅极，杂质区域形成在衬底的两侧的衬底中 栅极结构以及与浮动栅极间隔开并面对浮栅的导电层图案。 这种方法的实施例可以包括将编程电压施加到控制栅极，使杂质区域接地并且向导电层图案施加边缘电压以在浮动栅极中产生边缘场。

公开(公告)号：US20120235557A1

公开(公告)日：2012-09-20

申请号：US13291820

申请日：2011-11-08

申请人： Choong-Ho Lee

发明人： Choong-Ho Lee

IPC分类号： H01J19/58

CPC分类号： H01L51/5246

摘要： A display panel with secured mechanical reliability comprises: a first plate including a display region having light emitters and a non-display region, a second plate facing the first plate, a first frit portion interposed between the first plate and the second plate and sealing the display region from the outside, and a second frit portion separated from the first frit portion and comprising a plurality of sub-frits isolated from each other, wherein the sub-frits are located between a first line which passes through points closest to edges of the first plate among outer points of the first frit portion with respect to a sealed space and extends parallel to the edges of the first plate and a second line which passes through points furthest from the edges of the first plate among inner points of the first frit portion with respect to the sealed space and extends parallel to the edges of the first plate.

摘要翻译： 具有机械稳定性的显示面板包括：第一板，包括具有发光体和非显示区域的显示区域，与第一板材相对的第二板材，插入在第一板材和第二板材之间的第一玻璃料部分， 显示区域和与第一玻璃料部分分离并且包括彼此隔离的多个副玻璃料的第二玻璃料部分，其中子玻璃料位于通过最接近第二玻璃料边缘的点的第一条线之间 第一板在第一玻璃料部分的外部点之间相对于密封空间并且平行于第一板的边缘延伸，并且第二线在第一玻璃料部分的内部点之间穿过距离第一板的边缘最远的点 相对于密封空间并平行于第一板的边缘延伸。

公开(公告)号：US08158480B2

公开(公告)日：2012-04-17

申请号：US12213305

申请日：2008-06-18

申请人： Hee-Soo Kang ,  Choong-Ho Lee ,  Suk-Kang Sung ,  Se-Jun Park

发明人： Hee-Soo Kang ,  Choong-Ho Lee ,  Suk-Kang Sung ,  Se-Jun Park

IPC分类号： H01L21/336

CPC分类号： H01L27/11529 ,  H01L21/28273 ,  H01L27/105 ,  H01L27/11526 ,  H01L27/11531

摘要： A method of forming a semiconductor device pattern, a method of forming a charge storage pattern, a non-volatile memory device including a charge storage pattern and a method of manufacturing the same are provided. The method of forming the charge storage pattern including forming a trench on a substrate, and a device isolation pattern in the trench. The device isolation pattern protrudes from a surface of the substrate such that an opening exposing the substrate is formed. A tunnel oxide layer is formed on the substrate in the opening. A preliminary charge storage pattern is formed on the tunnel oxide layer and the device isolation pattern by selective deposition of conductive materials. The preliminary charge storage pattern may be removed from the device isolation pattern. The preliminary charge storage pattern remains only on the tunnel oxide layer to form the charge storage pattern on the substrate.

摘要翻译： 提供一种形成半导体器件图案的方法，形成电荷存储图案的方法，包括电荷存储图案的非易失性存储器件及其制造方法。 形成电荷存储图案的方法包括在衬底上形成沟槽，以及在沟槽中形成器件隔离图案。 器件隔离图案从衬底的表面突出出来，形成露出衬底的开口。 在开口中的基板上形成隧道氧化物层。 通过导电材料的选择性沉积，在隧道氧化物层和器件隔离图案上形成初步电荷存储图案。 初步电荷存储图案可以从器件隔离图案中去除。 初始电荷存储图案仅保留在隧道氧化物层上，以在基板上形成电荷存储图案。

公开(公告)号：US08120091B2

公开(公告)日：2012-02-21

申请号：US12128078

申请日：2008-05-28

申请人： Suk-Kang Sung ,  Choong-Ho Lee ,  Sang-wook Lim ,  Dong-Uk Choi ,  Hee-Soo Kang ,  Kyu-Charn Park

发明人： Suk-Kang Sung ,  Choong-Ho Lee ,  Sang-wook Lim ,  Dong-Uk Choi ,  Hee-Soo Kang ,  Kyu-Charn Park

IPC分类号： H01L29/788

CPC分类号： H01L21/28273 ,  H01L27/115 ,  H01L27/11521 ,  H01L29/42324

摘要： A non-volatile memory device includes a substrate and a tunnel insulation layer pattern, such that each portion of the tunnel insulation pattern extends along a first direction and adjacent portions of the tunnel insulation layer pattern may be separated in a second direction that is substantially perpendicular to the first direction. A non-volatile memory device may include a gate structure formed on the tunnel insulation layer pattern. The gate structure may include a floating gate formed on the tunnel insulation layer pattern along the second direction, a first conductive layer pattern formed on the floating gate in the second direction, a dielectric layer pattern formed on the first conductive layer pattern along the second direction, and a control gate formed on the dielectric layer pattern in the second direction.

摘要翻译： 非易失性存储器件包括衬底和隧道绝缘层图案，使得隧道绝缘图案的每个部分沿着第一方向延伸，并且隧道绝缘层图案的相邻部分可以在基本垂直的第二方向上分离 到第一个方向。 非易失性存储器件可以包括形成在隧道绝缘层图案上的栅极结构。 栅极结构可以包括沿着第二方向形成在隧道绝缘层图案上的浮动栅极，在第二方向上形成在浮置栅极上的第一导电层图案，沿着第二方向形成在第一导电层图案上的电介质层图案 以及在第二方向上形成在电介质层图案上的控制栅极。

公开(公告)号：US08053833B2

公开(公告)日：2011-11-08

申请号：US12622798

申请日：2009-11-20

申请人： Keun-Nam Kim ,  Hung-Mo Yang ,  Choong-Ho Lee

发明人： Keun-Nam Kim ,  Hung-Mo Yang ,  Choong-Ho Lee

IPC分类号： H01L27/088

CPC分类号： H01L29/7854 ,  H01L21/823412 ,  H01L21/823431 ,  H01L21/823481 ,  H01L27/0886 ,  H01L29/0653 ,  H01L29/0657 ,  H01L29/4236 ,  H01L29/66621 ,  H01L29/66795 ,  H01L29/7851 ,  H01L29/7856

摘要： A fin field effect transistor (fin FET) is formed using a bulk silicon substrate and sufficiently guarantees a top channel length formed under a gate, by forming a recess having a predetermined depth in a fin active region and then by forming the gate in an upper part of the recess. A device isolation film is formed to define a non-active region and a fin active region in a predetermined region of the substrate. In a portion of the device isolation film a first recess is formed, and in a portion of the fin active region a second recess having a depth shallower than the first recess is formed. A gate insulation layer is formed within the second recess, and a gate is formed in an upper part of the second recess. A source/drain region is formed in the fin active region of both sides of a gate electrode.

摘要翻译： 使用体硅衬底形成鳍状场效应晶体管（鳍FET），并通过在翅片有源区中形成具有预定深度的凹槽，然后通过在上部形成栅极来充分保证形成在栅极下方的顶部沟道长度 部分休息。 形成器件隔离膜以在衬底的预定区域中限定非有源区和鳍有源区。 在器件隔离膜的一部分中，形成第一凹部，并且在翅片有源区域的一部分中形成有比第一凹部浅的深度的第二凹部。 栅极绝缘层形成在第二凹部内，栅极形成在第二凹部的上部。 源极/漏极区域形成在栅电极的两侧的鳍片有源区域中。

公开(公告)号：US07978522B2

公开(公告)日：2011-07-12

申请号：US12416477

申请日：2009-04-01

申请人： Hee-Soo Kang ,  Dong-Uk Choi ,  Choong-Ho Lee ,  Sang-Gu Kang

发明人： Hee-Soo Kang ,  Dong-Uk Choi ,  Choong-Ho Lee ,  Sang-Gu Kang

IPC分类号： G11C11/34

CPC分类号： G11C11/5628 ,  G11C16/0483

摘要： A non-volatile memory device includes a selection transistor coupled to a bit line. The device also includes a plurality of memory cells serially coupled to the selection transistor and at least one dummy cell located between the plurality of memory cells. The dummy cell is turned off during a programming operation of a memory cell located between the dummy cell and the selection transistor.

摘要翻译： 非易失性存储器件包括耦合到位线的选择晶体管。 该装置还包括串联耦合到选择晶体管的多个存储单元和位于多个存储单元之间的至少一个虚拟单元。 在位于虚设单元和选择晶体管之间的存储单元的编程操作期间，虚设单元关闭。

公开(公告)号：US20110139357A1

公开(公告)日：2011-06-16

申请号：US12969365

申请日：2010-12-15

申请人： Choong-Ho Lee ,  Yoon-Chan Oh ,  Seung-Ho Choi ,  Suk-Won Jung ,  Jung-Soo Rhee

发明人： Choong-Ho Lee ,  Yoon-Chan Oh ,  Seung-Ho Choi ,  Suk-Won Jung ,  Jung-Soo Rhee

IPC分类号： B29C65/78 ,  B29C65/00

CPC分类号： C23C14/042 ,  B23K26/0846 ,  H01L51/56

摘要： A method of efficiently manufacturing a large-sized mask is disclosed. In one embodiment, the method includes: 1) providing a first mask member comprising i) a first pattern unit having a plurality of slits, ii) a first buffer unit spaced apart from the first pattern unit, and iii) a first bonding unit interconnecting the first pattern unit and the first buffer unit and 2) providing a second mask member comprising i) a second pattern unit having a plurality of slits, ii) a second buffer unit spaced apart from the second pattern unit, and iii) a second bonding unit interconnecting the second pattern unit and the second buffer unit. The method may further include contacting the first bonding unit and the second bonding unit; and connecting the first mask member to the second mask member while tensile forces are applied to the first mask member and the second mask member.

摘要翻译： 公开了一种有效地制造大尺寸掩模的方法。 在一个实施例中，该方法包括：1）提供第一掩模构件，其包括i）具有多个狭缝的第一图案单元，ii）与第一图案单元间隔开的第一缓冲单元，以及iii） 第一图案单元和第一缓冲单元，以及2）提供第二掩模构件，其包括i）具有多个狭缝的第二图案单元，ii）与第二图案单元间隔开的第二缓冲单元，以及iii）第二粘合 将第二图案单元和第二缓冲单元互连的单元。 该方法还可以包括使第一接合单元和第二接合单元接触; 以及当所述第一掩模构件和所述第二掩模构件施加张力时，将所述第一掩模构件连接到所述第二掩模构件。

公开(公告)号：US07919378B2

公开(公告)日：2011-04-05

申请号：US12397176

申请日：2009-03-03

申请人： Jae-Man Yoon ,  Choong-Ho Lee ,  Dong-Gun Park ,  Chul Lee

发明人： Jae-Man Yoon ,  Choong-Ho Lee ,  Dong-Gun Park ,  Chul Lee

IPC分类号： H01L21/336

CPC分类号： H01L29/785 ,  H01L29/66795

摘要： According to some embodiments of the invention, a fin type transistor includes an active structure integrally formed with a silicon substrate. The active structure includes grooves that form blocking regions under source/drain regions. A gate structure is formed to cross the upper face of the active structure and to cover the exposed side surfaces of the lateral portions of the active structure. An effective channel length of a fin type transistor may be sufficiently ensured so that a short channel effect of the transistor may be prevented and the fin type transistor may have a high breakdown voltage.

摘要翻译： 根据本发明的一些实施例，鳍型晶体管包括与硅衬底一体形成的有源结构。 活性结构包括在源极/漏极区域下形成阻挡区的沟槽。 栅极结构形成为跨越有源结构的上表面并且覆盖有源结构的侧部的暴露的侧表面。 可以充分确保翅片型晶体管的有效沟道长度，从而可以防止晶体管的短沟道效应，并且鳍式晶体管可能具有高击穿电压。