公开(公告)号：US07715248B2

公开(公告)日：2010-05-11

申请号：US12109081

申请日：2008-04-24

Applicant: John M. Aitken ,  Fen Chen ,  Kai D. Feng

Inventor： John M. Aitken ,  Fen Chen ,  Kai D. Feng

IPC: G11C7/00 ,  G11C7/22

CPC classification number: G11C11/56 ,  G11C11/5678 ,  G11C11/5692 ,  G11C13/0004 ,  G11C17/16 ,  G11C17/18 ,  H01L27/101 ,  H01L27/2409 ,  H01L45/06 ,  H01L45/1226 ,  H01L45/1233 ,  H01L45/145

Abstract: The present invention relates to a nonvolatile memory such as, for example a ROM or an EPROM, in which the information density of the memory is increased relative to a conventional nonvolatile memory that includes two logic state devices. Specifically, the nonvolatile memory of the present invention includes a SiN/TaN/SiN thin film resistor embedded within a material having a thermal conductivity of about 1 W/m-K or less; and a non-linear Si-containing device coupled to the resistor. Read and write circuits and operations are also provided in the present application.

Abstract translation: 本发明涉及诸如ROM或EPROM的非易失性存储器，其中存储器的信息密度相对于包括两个逻辑状态器件的常规非易失性存储器而增加。 具体地，本发明的非易失性存储器包括嵌入在热导率为约1W / m-K以下的材料中的SiN / TaN / SiN薄膜电阻器; 以及耦合到电阻器的非线性含Si器件。 读写电路和操作也在本申请中提供。

公开(公告)号：US20100035390A1

公开(公告)日：2010-02-11

申请号：US12188366

申请日：2008-08-08

Applicant: Hanyi Ding ,  Kai D. Feng ,  Zhong-Xiang He ,  Zhenrong Jin ,  Xuefeng Liu ,  Yun Shi

Inventor： Hanyi Ding ,  Kai D. Feng ,  Zhong-Xiang He ,  Zhenrong Jin ,  Xuefeng Liu ,  Yun Shi

IPC: H01L21/84

CPC classification number: H01L21/84 ,  H01L21/823462 ,  H01L21/823481 ,  H01L27/1203 ,  H01L27/1207

Abstract: A first portion of a top semiconductor layer of a semiconductor-on-insulator (SOI) substrate is protected, while a second portion of the top semiconductor layer is removed to expose a buried insulator layer. A first field effect transistor including a gate dielectric and a gate electrode located over the first portion of the top semiconductor layer is formed. A portion of the exposed buried insulator layer is employed as a gate dielectric for a second field effect transistor. In one embodiment, the gate electrode of the second field effect transistor is a remaining portion of the top semiconductor layer. In another embodiment, the gate electrode of the second field effect transistor is formed concurrently with the gate electrode of the first field effect transistor by deposition and patterning of a gate electrode layer.

Abstract translation: 保护绝缘体上半导体（SOI）衬底的顶部半导体层的第一部分，同时去除顶部半导体层的第二部分以暴露掩埋的绝缘体层。 形成包括位于顶部半导体层的第一部分上方的栅极电介质和栅电极的第一场效应晶体管。 暴露的掩埋绝缘体层的一部分用作第二场效应晶体管的栅极电介质。 在一个实施例中，第二场效应晶体管的栅电极是顶部半导体层的剩余部分。 在另一个实施例中，第二场效应晶体管的栅极通过栅极电极层的沉积和图案化与第一场效应晶体管的栅电极同时形成。

公开(公告)号：US20090317975A1

公开(公告)日：2009-12-24

申请号：US12144071

申请日：2008-06-23

Applicant: Hanyi Ding ,  Kai D. Feng ,  Zhong-Xiang He ,  Xuefeng Liu ,  Anthony K. Stamper

Inventor： Hanyi Ding ,  Kai D. Feng ,  Zhong-Xiang He ,  Xuefeng Liu ,  Anthony K. Stamper

IPC: H01L21/311

CPC classification number: H01L21/7682 ,  H01L21/3148 ,  H01L21/318 ,  H01L21/3185 ,  H01L27/0248

Abstract: A method for forming an on-chip high frequency electro-static discharge device is described. In one embodiment, a wafer with a multi-metal level wiring is provided and a hermetically sealed gap is formed therein to provide electro-static discharge protection for an integrated circuit.

Abstract translation: 描述形成片上高频静电放电装置的方法。 在一个实施例中，提供具有多金属水平布线的晶片，并且在其中形成气密密封的间隙以为集成电路提供静电放电保护。

公开(公告)号：US20090317970A1

公开(公告)日：2009-12-24

申请号：US12144089

申请日：2008-06-23

Applicant: Hanyi Ding ,  Kai D. Feng ,  Zhong-Xiang He ,  Xuefeng Liu ,  Anthony K. Stamper

Inventor： Hanyi Ding ,  Kai D. Feng ,  Zhong-Xiang He ,  Xuefeng Liu ,  Anthony K. Stamper

IPC: H01L21/4763

CPC classification number: H01L21/76808 ,  H01L21/7682 ,  H01L27/0248

Abstract: A method for forming an on-chip high frequency electro-static discharge device on an integrated circuit is described. In one embodiment of the method, a capped first dielectric layer with more than one electrode formed therein is provided. A second dielectric layer is deposited over the capped first dielectric layer. A first hard mask dielectric layer is deposited over the second dielectric layer. A cavity trench is formed through the first hard mask dielectric layer and the second dielectric layer to the first dielectric layer, wherein the cavity trench is formed in the first dielectric layer between two adjacent electrodes. At least one via is formed through the second dielectric layer about the cavity trench. A metal trench is formed around each of the at least one via. A release opening is formed over the cavity trench. A third dielectric layer is deposited over the second dielectric layer, wherein the third dielectric layer hermetically seals the release opening to provide electro-static discharge protection.

Abstract translation: 描述了在集成电路上形成片上高频静电放电装置的方法。 在该方法的一个实施例中，提供了一种其上形成有多于一个电极的封盖的第一电介质层。 在封盖的第一介电层上沉积第二介电层。 第一硬掩模介电层沉积在第二介电层上。 通过第一硬掩模电介质层和第二电介质层形成腔沟槽到第一介电层，其中在两个相邻电极之间的第一电介质层中形成空腔沟槽。 至少一个通孔围绕腔沟槽形成穿过第二电介质层。 在所述至少一个通孔中的每一个周围形成金属沟槽。 在空腔沟槽上形成释放开口。 在第二电介质层上沉积第三电介质层，其中第三介电层气密地密封释放开口以提供静电放电保护。

公开(公告)号：US20090316314A1

公开(公告)日：2009-12-24

申请号：US12144095

申请日：2008-06-23

Applicant: Hanyi Ding ,  Kai D. Feng ,  Zhong-Xiang He ,  Xuefeng Liu ,  Anthony K. Stamper

Inventor： Hanyi Ding ,  Kai D. Feng ,  Zhong-Xiang He ,  Xuefeng Liu ,  Anthony K. Stamper

IPC: H02H9/00 ,  G06F17/50

CPC classification number: H01L23/60 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A design structure for an on-chip high frequency electro-static discharge device is described. In one embodiment, the electro-static discharge structure comprises a first dielectric layer with more than one electrode formed therein. A second dielectric layer with more than one electrode formed therein is located above the first dielectric layer. At least one via connects the more than one electrode in the first dielectric layer with the more than one electrode in the second dielectric layer. A gap is formed through the first dielectric layer and the second dielectric layer, wherein the gap extends between two adjacent electrodes in both the first dielectric layer and the second dielectric layer. A third dielectric layer is disposed over the second dielectric layer, wherein the third dielectric layer hermetically seals the gap to provide electro-static discharge protection on the integrated circuit.

Abstract translation: 描述了片上高频静电放电装置的设计结构。 在一个实施例中，静电放电结构包括其中形成有多于一个电极的第一电介质层。 其中形成有多于一个电极的第二电介质层位于第一介电层的上方。 至少一个通孔将第一介电层中的多于一个的电极与第二介电层中的多于一个的电极连接。 通过第一电介质层和第二电介质层形成间隙，其中间隙在第一电介质层和第二电介质层中的两个相邻电极之间延伸。 第三电介质层设置在第二电介质层上，其中第三介电层气密地密封间隙以在集成电路上提供静电放电保护。

公开(公告)号：US07564319B2

公开(公告)日：2009-07-21

申请号：US11859850

申请日：2007-09-24

Applicant: Hanyi Ding ,  Kai D. Feng ,  Zhong-Xiang He ,  Xuefeng Liu

Inventor： Hanyi Ding ,  Kai D. Feng ,  Zhong-Xiang He ,  Xuefeng Liu

IPC: H03B5/08 ,  H01F5/00 ,  H01L29/00

CPC classification number: H03L7/099 ,  H01L23/5223 ,  H01L23/5225 ,  H01L23/5227 ,  H01L27/0617 ,  H01L27/0641 ,  H01L27/08 ,  H01L27/0811 ,  H01L28/10 ,  H01L2924/0002 ,  H03J3/20 ,  H01L2924/00

Abstract: An LC tack structure. The structure, including a set of wiring levels on top of a semiconductor substrate, the wiring levels stacked on top of each other from a lowest wiring level nearest the substrate to a highest wiring level furthest from the substrate; an inductor in the highest wiring level, the inductor confined within a perimeter of a region of the highest wiring level; and a varactor formed in the substrate, the varactor aligned completely under the perimeter of the region of the highest wiring level. The structure may additionally include an electric shield in a wiring level of the set of wiring levels between the lowest wiring level and the highest wiring level. Alternatively, the inductor includes a magnetic core and alternating electrically non-magnetic conductive metal coils and magnetic coils around the core.

Abstract translation: 一种LC粘结结构。 该结构包括在半导体衬底顶部的一组布线级别，从最靠近衬底的最低配线水平到离衬底最远的最高配线电平彼此堆叠的布线电平; 电感处于最高布线水平，电感器限制在最高布线水平的区域的周边内; 以及形成在基板中的变容二极管，变容二极管完全对准在最高布线水平的区域的周边。 该结构可以另外包括在最低布线电平和最高布线电平之间的布线级别的布线级中的电屏蔽。 或者，电感器包括磁芯和交替的非磁性导电金属线圈和围绕磁芯的磁性线圈。

公开(公告)号：US20080191716A1

公开(公告)日：2008-08-14

申请号：US11672535

申请日：2007-02-08

Applicant: Fen Chen ,  Kai D. Feng

Inventor： Fen Chen ,  Kai D. Feng

IPC: G01R27/26

CPC classification number: G01N27/223

Abstract: On-chip real-time moisture detection circuitry for monitoring ingress of moisture into an integrated circuit chip during the operational lifetime of the chip. The moisture detection circuitry includes one or more moisture-sensing units and a common moisture monitor for monitoring the state of each moisture-sensing units. The moisture monitor can be configured to provided a real-time moisture-detected signal for signaling that moisture ingress into the integrated circuit chip has occurred.

Abstract translation: 片上实时水分检测电路，用于在芯片的使用寿命期间监测水分进入集成电路芯片。 湿度检测电路包括一个或多个湿度感测单元和用于监测每个湿度感测单元的状态的公共湿度监视器。 水分监测器可以被配置为提供实时湿度检测信号，用于发信号通知已经发生湿气进入集成电路芯片。

公开(公告)号：US07030644B2

公开(公告)日：2006-04-18

申请号：US10771826

申请日：2004-02-03

Applicant: Kai D. Feng

Inventor： Kai D. Feng

IPC: H03K19/003

CPC classification number: H05K1/0246 ,  H03K19/0005 ,  H04L5/1423 ,  H04L25/0278 ,  H04L25/028 ,  H05K2201/09236 ,  H05K2201/10022

Abstract: A low reflection driver is provided for a high speed simultaneous bi-directional transmission line/data bus which is designed such that units at both ends of the transmission line/data bus can transmit data at any time without waiting for the bus to become available so that the baud rate of the bus is increased. A push-pull current source driver for the bi-directional simultaneous data bus provides greater flexibility for an output voltage swing, a matching impedance and bandwidth compensation.

Abstract translation: 为高速同步双向传输线/数据总线提供低反射驱动器，其设计使得传输线/数据总线两端的单元可以随时传输数据，而无需等待总线变得可用 巴士的波特率增加。 用于双向同步数据总线的推挽电流源驱动器为输出电压摆幅，匹配阻抗和带宽补偿提供了更大的灵活性。

公开(公告)号：US06834165B2

公开(公告)日：2004-12-21

申请号：US09774068

申请日：2001-01-31

Applicant: Kai D. Feng

Inventor： Kai D. Feng

IPC: H04B1006

CPC classification number: H04B10/69 ,  H04B10/6932

Abstract: An optical receiver circuit including a plurality of PIN diodes, each associated with a dedicated element transimpedance amplifier, the outputs of the element transimpedance amplifiers being connected to a summing amplifier which sums the voltages output from the element transimpedance amplifiers. The optical receiver circuit provides the same output voltage value as a single large PIN diode having an active area comparable to the sum of the active areas of the smaller PIN diodes, and thus has the same high sensitivity as the single large PIN diode but a much wider bandwidth.

Abstract translation: 一种光接收器电路，包括多个PIN二极管，每个PIN二极管与专用元件跨阻抗放大器相关联，元件跨阻抗放大器的输出端连接到求和放大器，该求和放大器将从元件跨阻放大器输出的电压相加。 光接收器电路提供与单个大PIN二极管相同的输出电压值，其具有与较小PIN二极管的有效面积之和相当的有效面积，因此具有与单个大PIN二极管相同的高灵敏度， 更宽的带宽。

公开(公告)号：US08941405B2

公开(公告)日：2015-01-27

申请号：US13566805

申请日：2012-08-03

Applicant: Howard H. Chi ,  Haitao O. Dai ,  Kai D. Feng ,  Donald J. Papae

Inventor： Howard H. Chi ,  Haitao O. Dai ,  Kai D. Feng ,  Donald J. Papae

IPC: H03K19/00 ,  H05K3/00

CPC classification number: G06F7/588 ,  G09C1/00 ,  H04L9/0866 ,  H04L9/3278 ,  H04L2209/12

Abstract: A FET pair based physically unclonable function (PUF) circuit with a constant common mode voltage and methods of use are disclosed. The circuit includes a first n-type field effect transistor (NFET) and a second NFET. The circuit also includes a first load resistor coupled to the first NFET by a first p-type field effect transistor (PFET) and a second load resistor coupled to the second NFET by a second PFET. The circuit further comprises a closed loop, wherein the closed loop creates a constant common mode voltage.

Abstract translation: 公开了一种具有恒定共模电压的物理不可克隆功能（PUF）电路和使用方法的FET对。 电路包括第一n型场效应晶体管（NFET）和第二NFET。 电路还包括通过第一p型场效应晶体管（PFET）耦合到第一NFET的第一负载电阻器和通过第二PFET耦合到第二NFET的第二负载电阻器。 电路还包括闭环，其中闭环产生恒定的共模电压。