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    SIGNAL PROCESSING CIRCUITRY WITH FRONTEND AND BACKEND CIRCUITRY CONTROLLED BY SEPARATE CLOCKS
    83.
    发明申请
    SIGNAL PROCESSING CIRCUITRY WITH FRONTEND AND BACKEND CIRCUITRY CONTROLLED BY SEPARATE CLOCKS 有权
    信号处理电路由分钟控制的FRONTEND和后端电路

    公开(公告)号：US20140181570A1

    公开(公告)日：2014-06-26

    申请号：US13724946

    申请日：2012-12-21

    Applicant: LSI CORPORATION

    Inventor： Suharli Tedja ,  Shaohua Yang ,  Fan Zhang ,  Qi Zuo ,  Joseph Garofalo ,  Yu Kou

    IPC: G06F1/06

    CPC classification number: G06F1/06 ,  G06F1/08 ,  G06F1/206

    Abstract: An apparatus comprises read channel circuitry and associated signal processing circuitry comprising frontend processing circuitry and backend processing circuitry. The frontend processing circuitry comprises a loop detector and equalizer configured to determine an equalized read channel signal from a read channel signal and a decoding module configured to apply verification and scrambling processing on a decoded read channel signal. The backend processing circuitry comprises a backend detector, an interleaver, a backend decoder, and a de-interleaver configured to perform an iterative decoding process on the equalized read channel signal to determine the decoded read channel signal. The frontend processing circuitry is controlled by a first clock having an associated first clock rate and the backend processing circuitry is controlled by a selected one of the first clock and a second clock having an associated second clock rate determined at least in part by the first clock rate and a maximum clock rate.

    Abstract translation: 一种装置包括读通道电路和包括前端处理电路和后端处理电路的相关信号处理电路。 前端处理电路包括环路检测器和均衡器，其被配置为从读取信道信号确定均衡的读取信道信号，以及解码模块，被配置为对解码的读取信道信号进行验证和加扰处理。 后端处理电路包括后端检测器，交织器，后端解码器和解交织器，被配置为对均衡的读信道信号执行迭代解码处理，以确定解码的读信道信号。 前端处理电路由具有相关联的第一时钟速率的第一时钟控制，并且后端处理电路由第一时钟中所选择的一个控制，第二时钟具有至少部分地由第一时钟确定的相关联的第二时钟速率 速率和最大时钟速率。

    Irregular Low Density Parity Check Decoder With Low Syndrome Error Handling
    84.
    发明申请
    Irregular Low Density Parity Check Decoder With Low Syndrome Error Handling 有权
    具有低综合征错误处理的不规则低密度奇偶校验解码器

    公开(公告)号：US20140168811A1

    公开(公告)日：2014-06-19

    申请号：US13777381

    申请日：2013-02-26

    Applicant: LSI CORPORATION

    Inventor： Shaohua Yang ,  Anatoli A. Bolotov ,  Chung-Li Wang ,  Zongwang Li ,  Shu Li ,  Mikhail I. Grinchuk

    IPC: H03M13/13 ,  G11B20/18

    CPC classification number: G11B20/18 ,  G11B20/1833 ,  G11B2020/185 ,  H03M13/09 ,  H03M13/1111 ,  H03M13/1128 ,  H03M13/27 ,  H03M13/6331

    Abstract: A data processing system is disclosed including a data decoder circuit, an error handling circuit and a syndrome checker circuit. The data decoder circuit is operable to apply a data decode algorithm to a decoder input to yield a decoded output, and to calculate a syndrome indicating an error level for the decoded output. The error handling circuit is operable to determine whether any errors in the decoded output involve user data bits. The syndrome checker circuit is operable to trigger the error handling circuit based at least in part on the syndrome.

    Abstract translation: 公开了一种数据处理系统，包括数据解码器电路，错误处理电路和综合检查电路。 数据解码器电路可操作以将数据解码算法应用于解码器输入以产生解码输出，并计算指示解码输出的误差电平的校正子。 错误处理电路可操作以确定解码输出中的任何错误是否涉及用户数据位。 综合征检查器电路可操作以至少部分地基于综合征来触发误差处理电路。

    Systems and Methods for Partially Conditioned Noise Predictive Equalization
    85.
    发明申请
    Systems and Methods for Partially Conditioned Noise Predictive Equalization 审中-公开
    部分条件噪声预测均衡的系统和方法

    公开(公告)号：US20140129603A1

    公开(公告)日：2014-05-08

    申请号：US14152917

    申请日：2014-01-10

    Applicant: LSI Corporation

    Inventor： Shaohua Yang ,  Haitao Xia

    IPC: H03H17/02

    CPC classification number: H03H17/0248 ,  G11B20/10046 ,  H04L25/03012 ,  H04L25/03203 ,  H04L25/03299 ,  H04L25/03993

    Abstract: Various embodiments of the present invention provide systems and methods for equalization. As an example, a circuit for data equalization is described that includes a 2N state detector circuit that provides a series of detected bits based upon a conditioned input, and a noise predictive filter having a plurality of taps and operable to provide at least a portion of the conditioned input. At least a first of the plurality of taps uses a first subset of the series of detected bits, and a second of the plurality of taps uses a second subset of the series of detected bits. The first subset of the detected bits includes one more bit than the second subset of the detected bits.

    Abstract translation: 本发明的各种实施例提供用于均衡的系统和方法。 作为示例，描述了用于数据均衡的电路，其包括2N状态检测器电路，其基于经调节的输入提供一系列检测到的位，以及具有多个抽头的噪声预测滤波器，并且可操作以提供至少一部分 条件输入。 所述多个抽头中的至少第一个抽头使用所述一系列检测到的位的第一子集，并且所述多个抽头中的第二个抽头使用所述一系列检测到的位的第二子集。 检测到的比特的第一子集比检测到的比特的第二子集多一个比特。

    Systems and methods for recovered data stitching
    86.
    发明授权
    Systems and methods for recovered data stitching 有权
    恢复数据拼接的系统和方法

    公开(公告)号：US09400797B2

    公开(公告)日：2016-07-26

    申请号：US14047319

    申请日：2013-10-07

    Applicant: LSI Corporation

    Inventor： Shaohua Yang ,  Xuebin Wu ,  Shu Li

    IPC: G06F11/00 ,  H03M13/00 ,  G06F17/30 ,  G06F11/08 ,  G06F11/10 ,  G11B20/10 ,  G11B20/18

    CPC classification number: G06F17/30135 ,  G06F11/085 ,  G06F11/1076 ,  G11B20/10009 ,  G11B20/10268 ,  G11B20/18 ,  G11B20/1866

    Abstract: Systems and method relating generally to data processing, and more particularly to systems and methods for combining recovered portions of a data set. In one particular case, a system is disclosed that includes a stitching circuit and a data recovery circuit. The stitching circuit is operable to: receive a data set including at least a first fragment and a second fragment; replicate data from at least one of the first fragment and the second fragment as stitching values; and aggregate the first fragment with the second fragment with the stitching values between the first fragment and the second fragment to yield a combined data set. The data recovery circuit is operable to process the combined data set to yield an original data set.

    Abstract translation: 一般涉及数据处理的系统和方法，更具体地涉及用于组合数据集的恢复部分的系统和方法。 在一个特定情况下，公开了一种包括缝合电路和数据恢复电路的系统。 缝合电路可操作以：接收包括至少第一片段和第二片段的数据集; 将来自第一片段和第二片段中的至少一个的数据复制为拼接值; 并且将具有第二片段的第一片段与第一片段和第二片段之间的缝合值聚合以产生组合数据集。 数据恢复电路可操作以处理组合数据集以产生原始数据集。

    Modify priority of dataset based on number of times the data set is processed by both a data detector circuit and a data decoder circuit
    89.
    发明授权
    Modify priority of dataset based on number of times the data set is processed by both a data detector circuit and a data decoder circuit 有权
    基于由数据检测器电路和数据解码器电路处理数据集的次数来修改数据集的优先级

    公开(公告)号：US09298369B2

    公开(公告)日：2016-03-29

    申请号：US13766874

    申请日：2013-02-14

    Applicant: LSI Corporation

    Inventor： Shaohua Yang ,  Fan Zhang ,  Jun Xiao ,  Kaitlyn T. Nguyen

    IPC: G06F9/46 ,  G06F3/06

    CPC classification number: G06F3/06 ,  G11B20/10009 ,  G11B20/10268 ,  G11B20/10305 ,  G11B20/10527

    Abstract: Systems, circuits, devices and/or methods related to systems and methods for data processing, and more particularly to systems and methods for quality based scheduling processing of data sets. In some cases, a priority indication associated with a data set is modified based upon one or more factors. As an example, the priority indication may be modified based upon a number of times that a given data set processed through both a data detector circuit and a data decoder circuit.

    Abstract translation: 与用于数据处理的系统和方法相关的系统，电路，设备和/或方法，更具体地涉及用于数据集的基于质量的调度处理的系统和方法。 在一些情况下，基于一个或多个因素修改与数据集相关联的优先指示。 作为示例，可以基于通过数据检测器电路和数据解码器电路来处理的给定数据集的次数来修改优先级指示。

    Read channel sampling utilizing two quantization modules for increased sample bit width
    90.
    发明授权
    Read channel sampling utilizing two quantization modules for increased sample bit width 有权
    使用两个量化模块读取通道采样以增加采样位宽度

    公开(公告)号：US09281007B2

    公开(公告)日：2016-03-08

    申请号：US14198008

    申请日：2014-03-05

    Applicant: LSI Corporation

    Inventor： Xuebin Wu ,  Yang Han ,  Weijun Tan ,  Shaohua Yang

    IPC: G11B20/10 ,  G11B20/14 ,  G11B5/55 ,  G11B5/012 ,  G10L19/02

    CPC classification number: G11B20/10046 ,  G10L19/0208 ,  G11B5/012 ,  G11B5/5526 ,  G11B5/553 ,  G11B20/10009 ,  G11B20/10268 ,  G11B20/1403

    Abstract: A communication channel structure and a decoding method supported by such a communication channel structure are disclosed. Such a communication channel includes a digital filter configured for filtering an input signal and two quantizer configured for quantizing the filtered signal. A first quantizer is utilized to quantize the filtered signal to produce a first quantized sample having a first precision and a second quantizer is utilized to quantize the filtered signal to produce a second quantized sample having a second precision, wherein the second precision is different from the first precision. The communication channel also includes an iterative decoder configured for utilizing the first quantized sample for a first global iteration of a decoding process and utilizing the second quantized sample for at least one subsequent global iteration of the decoding process.

    Abstract translation: 公开了一种由这种通信信道结构支持的通信信道结构和解码方法。 这样的通信信道包括被配置为对输入信号进行滤波的数字滤波器和被配置为量化滤波信号的两个量化器。 利用第一量化器来量化滤波后的信号以产生具有第一精度的第一量化样本，并且使用第二量化器量化滤波信号以产生具有第二精度的第二量化样本，其中第二精度不同于 第一精度。 通信信道还包括迭代解码器，其被配置为利用第一量化样本进行解码过程的第一全局迭代，并且利用第二量化样本进行解码过程的至少一个后续全局迭代。

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