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    TWO TRANSISTOR CELLS FOR VERTICAL THREE-DIMENSIONAL MEMORY HAVING VERICAL DIGIT LINES
    81.
    发明公开
    TWO TRANSISTOR CELLS FOR VERTICAL THREE-DIMENSIONAL MEMORY HAVING VERICAL DIGIT LINES 审中-公开

    公开(公告)号：US20240357794A1

    公开(公告)日：2024-10-24

    申请号：US18645043

    申请日：2024-04-24

    Applicant: Micron Technology, Inc.

    Inventor： Litao Yang ,  Haitao Liu ,  Kamal M. Karda ,  Si-Woo Lee

    IPC: H10B12/00

    CPC classification number: H10B12/00

    Abstract: Systems, methods and apparatus are provided for two transistor cells for vertical three-dimensional memory. The memory has pairs of serially connected transistors, each pair of serially connected transistors having an independent first source/drain region and a shared second source/drain region separated by channel regions; horizontally oriented access lines separated from the channel regions by a gate dielectric material; and vertically oriented digit lines electrically coupled to the first source/drain regions of the serially connected transistors.

    MEMORY DEVICE HAVING TIERS OF MEMORY CELLS AND ACCESS LINE HAVING MULTIPLE CONDUCTIVE REGIONS
    82.
    发明公开
    MEMORY DEVICE HAVING TIERS OF MEMORY CELLS AND ACCESS LINE HAVING MULTIPLE CONDUCTIVE REGIONS 审中-公开

    公开(公告)号：US20240274194A1

    公开(公告)日：2024-08-15

    申请号：US18435434

    申请日：2024-02-07

    Applicant: Micron Technology, Inc.

    Inventor： Kamal M. Karda ,  Si-Woo Lee ,  Haitao Liu

    IPC: G11C16/04 ,  G11C5/06 ,  H10B41/27

    CPC classification number: G11C16/0483 ,  G11C5/063 ,  H10B41/27

    Abstract: Some embodiments include apparatuses in which one of the apparatuses includes a first conductive structure, a second conductive structure, a third conductive structure, and a memory cell. The memory cell includes a semiconductor portion located on a first level of the apparatus and coupled to the first conductive structure, and a charge storage structure located on the first level coupled to the semiconductor portion and separated from the second conductive structure. The third conductive structure is located on a second level of the apparatus adjacent the semiconductor portion, and including first, second, and third conductive regions. The third conductive region is located between the first and second conductive regions and has a material different from a material of the first conductive region and a material of the second conductive region.

    RECESSED CHANNEL FIN INTEGRATION
    85.
    发明公开
    RECESSED CHANNEL FIN INTEGRATION 审中-公开

    公开(公告)号：US20240057317A1

    公开(公告)日：2024-02-15

    申请号：US17886917

    申请日：2022-08-12

    Applicant: Micron Technology, Inc.

    Inventor： Sangmin Hwang ,  Si-Woo Lee

    IPC: H01L27/108

    CPC classification number: H01L27/10826 ,  H01L27/10897 ,  H01L27/10879

    Abstract: A variety of applications can include apparatus having a recessed channel FinFET. The recessed channel FinFET can include one or more fin structures between the source region and the drain region, where the one or more fin structures are recessed from a top level of the source region and from a top level of the drain region. The recessed channel FinFET can include a gate recessed from the top level of a source region and a drain region, where the gate can be separated from tip regions of the fin structures by a gate dielectric defining a channel between the source region and the drain region. Recessed channel FinFETs can be structured in a periphery to an array of a memory device and can be fabricated in a process merged with forming access lines to the array.

    Epitaxial silicon within horizontal access devices in vertical three dimensional (3D) memory
    89.
    发明授权
    Epitaxial silicon within horizontal access devices in vertical three dimensional (3D) memory 有权

    公开(公告)号：US11469232B2

    公开(公告)日：2022-10-11

    申请号：US17171336

    申请日：2021-02-09

    Applicant: Micron Technology, Inc.

    Inventor： Si-Woo Lee

    IPC: H01L27/108 ,  H01L21/762

    Abstract: Systems, methods and apparatus are provided for an array of vertically stacked memory cells having horizontally oriented access devices and storage nodes. The horizontally oriented access devices having a first source/drain regions and a second source drain regions separated by epitaxially grown channel regions. Gates opposing the channel regions formed fully around every surface of the channel region as gate all around (GAA) structures separated from a channel regions by a gate dielectrics. The memory cells have horizontally oriented storage nodes coupled to the second source/drain regions and digit lines coupled to the first source/drain regions.

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