公开(公告)号：US07590968B1

公开(公告)日：2009-09-15

申请号：US11680552

申请日：2007-02-28

申请人： Scott T. Becker ,  Michael C. Smayling

发明人： Scott T. Becker ,  Michael C. Smayling

IPC分类号： G06F17/50

CPC分类号： G06F17/5068 ,  G06F17/5072

摘要： A chip layout is generated based on a quantified fabrication process capability. A minimum required value is selected for a fabrication process capability factor associated with a fabrication process to be performed on a layer sub-region within the chip. Design rules are determined for the layer sub-region within the chip that will enable the selected minimum required value for the fabrication process capability factor associated with the layer sub-region to be satisfied. A layout is then generated for the layer sub-region within the chip using the determined design rules associated with the layer sub-region. Fabrication process capability can be improved by restricting the design rules and generated layouts to a linear design style that requires features defined within the chip to be linear in shape and without bends. The linear design style enables optimization of photolithographic rendering without the need to consider two-dimensional optical effects.

摘要翻译： 基于量化的制造工艺能力产生芯片布局。 选择与在芯片内的层子区域执行的制造工艺相关联的制造工艺能力因素的最小所需值。 确定芯片内的层子区域的设计规则，使得能够满足与层子区域相关联的制造工艺能力因素所选择的最小所需值。 然后使用与层子区域相关联的确定的设计规则为芯片内的层子区域生成布局。 可以通过将设计规则和生成的布局限制为线性设计风格来提高制造工艺能力，该线性设计风格需要在芯片内定义的特征是线性的，没有弯曲。 线性设计风格可以优化光刻渲染，而无需考虑二维光学效果。

公开(公告)号：US20090127636A1

公开(公告)日：2009-05-21

申请号：US12271907

申请日：2008-11-16

申请人： Michael C. Smayling ,  Scott T. Becker

发明人： Michael C. Smayling ,  Scott T. Becker

IPC分类号： H01L29/78 ,  H01L21/04 ,  G06F17/50

CPC分类号： H01L29/1041 ,  H01L21/823807 ,  H01L27/0207

摘要： A transistor is defined to include a substrate portion and a diffusion region defined in the substrate portion so as to provide an operable transistor threshold voltage. An implant region is defined within a portion of the diffusion region so as to transform the operable transistor threshold voltage of the diffusion region portion into an inoperably high transistor threshold voltage. A gate electrode is defined to extend over both the diffusion region and the implant region. A first portion of the gate electrode defined over the diffusion region forms a first transistor segment having the operable transistor threshold voltage. A second portion of the gate electrode defined over the implant region forms a second transistor segment having the inoperably high transistor threshold voltage. Therefore, a boundary of the implant region defines a boundary of the operable first transistor segment.

摘要翻译： 晶体管被限定为包括限定在衬底部分中的衬底部分和扩散区域，以便提供可操作的晶体管阈值电压。 注入区域被限定在扩散区域的一部分内，以便将扩散区域部分的可操作的晶体管阈值电压转换成不可操作的高晶体管阈值电压。 限定栅电极以在扩散区域和植入区域两者上延伸。 限定在扩散区上的栅电极的第一部分形成具有可操作的晶体管阈值电压的第一晶体管段。 限定在注入区域上的栅电极的第二部分形成具有不可操作的高晶体管阈值电压的第二晶体管段。 因此，注入区域的边界限定可操作的第一晶体管段的边界。

公开(公告)号：US20090100396A1

公开(公告)日：2009-04-16

申请号：US12340406

申请日：2008-12-19

申请人： Michael C. Smayling ,  Michael A. McAweeney ,  Scott T. Becker

发明人： Michael C. Smayling ,  Michael A. McAweeney ,  Scott T. Becker

IPC分类号： G06F17/50

CPC分类号： G06F17/5068 ,  G03F1/36

摘要： Selected cells in a semiconductor chip layout are replaced with corresponding PCT pre-processed cells. Each PCT pre-processed cell represents a particular selected cell having been previously subjected to a cell-level-PCT-processing operation so as to include PCT-based cell layout adjustments. Following replacement of the selected cells in the semiconductor chip layout with corresponding PCT pre-processed cells, a chip-wide PCT processing operation is performed on the semiconductor chip layout for a given chip level. The presence of the PCT pre-processed cells in the semiconductor chip layout serves to accelerate the chip-wide PCT processing of the semiconductor chip layout. The chip-wide PCT processed semiconductor layout for the given chip level is recorded on a persistent storage medium.

摘要翻译： 半导体芯片布局中的选定单元被相应的PCT预处理单元替换。 每个PCT预处理小区表示先前已经进行细胞级PCT处理操作的特定选择的细胞，以便包括基于PCT的细胞布局调整。 在用相应的PCT预处理单元替换半导体芯片布局中的所选单元之后，针对给定的芯片级对半导体芯片布局执行芯片宽的PCT处理操作。 半导体芯片布局中的PCT预处理电池的存在用于加速半导体芯片布局的芯片宽的PCT处理。 用于给定芯片级的芯片宽的PCT处理的半导体布局被记录在永久存储介质上。

公开(公告)号：US20090066358A1

公开(公告)日：2009-03-12

申请号：US12205871

申请日：2008-09-06

申请人： Michael C. Smayling ,  Shiany Oemardani ,  Karl F. Smayling

发明人： Michael C. Smayling ,  Shiany Oemardani ,  Karl F. Smayling

IPC分类号： G01R31/26

CPC分类号： G01R31/2858 ,  G01R31/2853 ,  H01L22/34 ,  H01L2924/0002 ,  H01L2924/00

摘要： In some aspects, a method is provided for detecting a void in a test structure that comprises (a) measuring a resistance of the test structure; (b) applying a stress to the test structure at increasing levels until at least one of: (i) the measured resistance of the test structure exceeds a predetermined resistance threshold; and (ii) the stress level reaches a predetermined stress maximum; (c) detecting a void if the measured resistance of the test structure exceeds the predetermined resistance threshold; and (d) determining that the test structure is void free if the stress level reaches the predetermined stress maximum without the measured resistance of the test structure exceeding the predetermined resistance threshold. Numerous other aspects are provided.

摘要翻译： 在一些方面，提供了一种用于检测测试结构中的空隙的方法，其包括：（a）测量测试结构的电阻; （b）以增加的水平向测试结构施加应力，直到以下至少一个：（i）测试结构的测量电阻超过预定电阻阈值; 和（ii）应力水平达到预定的应力最大值; （c）如果测试结构的测量电阻超过预定电阻阈值，则检测空隙; 以及（d）如果应力水平达到预定的应力最大值而确定测试结构无空隙，而测试结构的测量电阻不超过预定电阻阈值。 提供了许多其他方面。

公开(公告)号：US20090032967A1

公开(公告)日：2009-02-05

申请号：US12013342

申请日：2008-01-11

申请人： Scott T. Becker ,  Michael C. Smayling

发明人： Scott T. Becker ,  Michael C. Smayling

IPC分类号： H01L23/528

CPC分类号： H01L27/11807 ,  G06F17/5068 ,  G06F2217/12 ,  H01L23/5226 ,  H01L23/528 ,  H01L27/0207 ,  H01L27/11803 ,  H01L2027/1182 ,  H01L2027/11866 ,  H01L2027/11874 ,  H01L2027/11888 ,  Y02P90/265

摘要： A semiconductor chip is provided to include one or more distinct but functionally interfaced dynamic array sections. Each dynamic array section follows a dynamic array architecture that requires conductive features to be linearly defined along a virtual grate in each of a plurality of levels of the semiconductor chip. Each virtual grate is perpendicular to another virtual grate that is either a level above or a level below. Each virtual grate is defined by a framework of parallel lines spaced at a constant pitch. Some of the lines in the virtual grate are occupied by multiple conductive features. A substantially uniform gap can be maintained between proximate ends of adjacent conductive features that occupy a common line in the virtual grate. The substantially uniform gap between the proximate ends of adjacent conductive features can be maintained within each line in the virtual grate that is occupied by multiple conductive features.

摘要翻译： 提供半导体芯片以包括一个或多个不同但功能上接合的动态阵列部分。 每个动态阵列部分遵循动态阵列架构，其需要沿着半导体芯片的多个级别中的每一层中的虚拟栅格线性地限定导电特征。 每个虚拟炉排垂直于另一个虚拟炉排，其高于或低于水平。 每个虚拟格栅由以恒定间距间隔开的平行线的框架限定。 虚拟炉排中的一些线路被多个导电特征所占据。 可以在占据虚拟炉排中的公共线的相邻导电特征的近端之间保持基本均匀的间隙。 相邻导电特征的近端之间的基本均匀的间隙可以保持在由多个导电特征占据的虚拟格栅中的每一行内。

公开(公告)号：US06246102B1

公开(公告)日：2001-06-12

申请号：US08485412

申请日：1995-06-07

申请人： Roland Sauerbrey ,  Michael C. Smayling

发明人： Roland Sauerbrey ,  Michael C. Smayling

IPC分类号： H01L2978

CPC分类号： H01L23/5328 ,  H01B1/12 ,  H01B1/128 ,  H01L21/485 ,  H01L23/5254 ,  H01L2924/0002 ,  H01L2924/09701 ,  H01L2924/12044 ,  H05K3/105 ,  H05K3/4038 ,  H05K2201/0329 ,  H05K2203/107 ,  H05K2203/1136 ,  H01L2924/00

摘要： An integrated circuit includes conductive elements and a radiation sensitive material interposed between the conductive elements and dosed to different conductivities in different portions thereof. Another aspect is a process of integrated circuit fabrication including steps of depositing a radiation sensitive material as a layer and variably dosing it with radiation to establish areas of higher and lower resistivity in the layer. A printed wiring board includes radiation sensitive material and the board further has a conductor layer affixed to the base. A transistor has a radiation sensitive material dosed to have two conductive regions separated by a gap of a lower conductivity in the radiation sensitive material, and a conductive substance deposited over the gap. These elements are useful in smart power devices, digital computers, controllers and electronic applications generally. Other devices, systems and processes are disclosed.

摘要翻译： 集成电路包括介于导电元件之间的导电元件和辐射敏感材料，并且在其不同部分中被赋予不同的电导率。 另一方面是集成电路制造的过程，包括将辐射敏感材料沉积为层并且可变地对辐射进行配量的步骤，以在层中建立更高和更低电阻率的区域。 印刷电路板包括辐射敏感材料，并且板还具有固定到基底的导体层。 晶体管具有放射敏感材料，其具有由辐射敏感材料中较低导电性的间隙隔开的两个导电区域，以及沉积在间隙上的导电物质。 这些元件通常用于智能功率器件，数字计算机，控制器和电子应用中。 公开了其他设备，系统和过程。

公开(公告)号：US5815026A

公开(公告)日：1998-09-29

申请号：US684607

申请日：1996-07-19

申请人： Giovanni Santin ,  Giulio Marotta ,  Michael C. Smayling

发明人： Giovanni Santin ,  Giulio Marotta ,  Michael C. Smayling

IPC分类号： H02M3/07 ,  H02M3/18 ,  H02M7/00

CPC分类号： H02M3/073 ,  H02M2003/078

摘要： An integrated circuit voltage multiplier 30 in a semiconductor substrate of a first conductivity type. The multiplier includes a diode 22, having a first voltage VDD applied to a first port thereof, the diode being made of: 1) a first well 12 of a second conductivity type formed in the substrate, being connected to a second voltage VB; 2) a second well 14 of the first conductivity type formed in the first well, having an electrical contact point comprising the first port of the diode; and 3) a third well 16 of the second conductivity type formed in the second well, having an electrical contact point comprising a second port of the diode. The multiplier also includes a capacitor C3, having a first contact thereof connected to the second port of the diode and having a third, pulsed voltage PH1 connected to a second contact of the capacitor. The second voltage has a value of the first voltage or higher, such that the emitter-base junction of a parasitic transistor 20 formed by the substrate, the first well and the second well is not forward biased, and wherein the third, pulsed voltage drives the second port of the diode to a voltage of a level of the first voltage, less the forward bias voltage drop of the diode, plus the level of the third voltage.

摘要翻译： 在第一导电类型的半导体衬底中的集成电路电压倍增器30。 乘法器包括二极管22，其具有施加到其第一端口的第一电压VDD，二极管由以下构成：1）形成在衬底中的第二导电类型的第一阱12，连接到第二电压VB; 2）形成在第一阱中的第一导电类型的第二阱14，具有包括二极管的第一端口的电接触点; 和3）形成在第二阱中的第二导电类型的第三阱16，具有包括二极管的第二端口的电接触点。 乘法器还包括电容器C3，其具有连接到二极管的第二端口的第一触点，并具有连接到电容器的第二触点的第三脉冲电压PH1。 第二电压具有第一电压或更高的值，使得由衬底，第一阱和第二阱形成的寄生晶体管20的发射极 - 基极结不被正向偏置，并且其中第三脉冲电压驱动 二极管的第二个端口为第一电压电平的电压，二极管的正向偏置电压降，加上第三电压的电平。

公开(公告)号：US5665991A

公开(公告)日：1997-09-09

申请号：US456238

申请日：1995-05-31

申请人： Taylor R. Efland ,  Satwinder Malhi ,  Michael C. Smayling ,  Joseph A. Devore ,  Ross E. Teggatz ,  Alec J. Morton

发明人： Taylor R. Efland ,  Satwinder Malhi ,  Michael C. Smayling ,  Joseph A. Devore ,  Ross E. Teggatz ,  Alec J. Morton

IPC分类号： H01L23/482 ,  H01L23/528 ,  H01L29/417 ,  H01L29/78 ,  H01L23/522

CPC分类号： H01L23/5286 ,  H01L23/4824 ,  H01L29/41725 ,  H01L29/41758 ,  H01L29/7816 ,  H01L29/7835 ,  H01L2924/0002

摘要： The device has a semiconductor chip having active circuitry in the face thereof. The circuitry has busing over it containing two conductive layers having a plurality of contacts and vias with spacings between them that alternate with respect to one another to provide current ballasting and improved switching uniformity. The spacings between the alternating contacts and vias provide regions of maximum conductor thickness and therefore reduces the busing resistance. Staggering the rows of alternating contacts and vias provides further current ballasting. A first conducting layer is used to contact and provide electrically isolated low resistive conducting paths to the various semiconductor regions while the second conducting region is used to provide selective contact to the first conductive layer, thus providing a means of busing large currents over active semiconductor area without sacrificing performance parameters.

摘要翻译： 该器件具有在其表面上具有有源电路的半导体芯片。 该电路具有引线，其中包含两个具有多个触点的导电层和在它们之间具有相互间交替的间隙的通孔，以提供电流镇流和改善的开关均匀性。 交替触点和通孔之间的间距提供最大导体厚度的区域，因此降低了阻抗。 交错的交替触点和通孔的排列提供了进一步的电流镇流。 第一导电层用于接触并提供到各种半导体区域的电隔离的低电阻导电路径，而第二导电区域用于提供与第一导电层的选择性接触，从而提供在有源半导体区域上引入大电流的装置 而不牺牲性能参数。

公开(公告)号：US5567550A

公开(公告)日：1996-10-22

申请号：US37050

申请日：1993-03-25

申请人： Michael C. Smayling

发明人： Michael C. Smayling

IPC分类号： G03F1/00 ,  G03F7/00 ,  G03F7/09 ,  H01L51/00 ,  H01L51/30 ,  H01L51/40 ,  H05K1/16 ,  G03F9/00

CPC分类号： H01L51/0508 ,  G03F7/094 ,  H01L27/283 ,  H01L51/0014 ,  H01L51/002 ,  H01L51/0035 ,  H01L51/0512 ,  H01L51/0516 ,  H01L51/0587 ,  H01L51/0013 ,  H05K1/16 ,  Y10S428/901 ,  Y10T428/24942 ,  Y10T428/24975

摘要： A transistor device 10 is disclosed herein. A doped layer 14 of a radiation sensitive material is formed over a substrate 12. The radiation sensitive material 14 may be polyimide, polybenzimidazole, a polymer, an organic dielectrics, a conductor or a semiconductor and the substrate 12 may be silicon, quartz, gallium arsenide, glass, ceramic, metal or polyimide. A neutral (undoped) layer 16 of radiation sensitive material is formed over the doped layer 14. First and second source/drain regions 18 and 20 are formed in the neutral layer 16 and extend to a top portion of the doped layer 14. A gate region 22 is formed in a top portion of the neutral layer 16 between the first source/drain region 18 and second source/drain region 20 such that a channel region 24 is formed in the doped layer 14 beneath the gate region 22.

摘要翻译： 本文公开了晶体管器件10。 辐射敏感材料的掺杂层14形成在衬底12上。辐射敏感材料14可以是聚酰亚胺，聚苯并咪唑，聚合物，有机电介质，导体或半导体，并且衬底12可以是硅，石英，镓 砷化物，玻璃，陶瓷，金属或聚酰亚胺。 在掺杂层14上形成辐射敏感材料的中性（未掺杂）层16.第一和第二源/漏区18和20形成在中性层16中并延伸到掺杂层14的顶部。门 区域22形成在第一源极/漏极区域18和第二源极/漏极区域20之间的中性层16的顶部，使得沟道区24形成在栅极区域22下方的掺杂层14中。

公开(公告)号：US5557569A

公开(公告)日：1996-09-17

申请号：US453474

申请日：1995-05-25

申请人： Michael C. Smayling ,  Giulio G. Marotta ,  Iano D'Arrigo ,  Giovanni Santin ,  Georges Falessi ,  Mousumi Bhat

发明人： Michael C. Smayling ,  Giulio G. Marotta ,  Iano D'Arrigo ,  Giovanni Santin ,  Georges Falessi ,  Mousumi Bhat

IPC分类号： G11C16/04 ,  G11C16/08 ,  H01L27/115

CPC分类号： G11C16/0416 ,  G11C16/0433 ,  G11C16/08 ,  H01L27/115

摘要： A low voltage flash EEPROM X-Cell includes an array of memory cell transistors (24) that constitute asymmetric floating gate memory cells wherein programming is achieved on only one side of the memory cells (24). The programming side of each of the memory cells (24) is connected to one of a plurality of Column Lines (28) at nodes (30). Each node (30) shares the programming side of two of the memory cells (24) and the non-programming side of two of the memory cells (24). The control gates of each of the memory cells (24) are connected to Word Lines (26) associated with rows of the array. To Flash Write all of the memory cells (24), the Column Lines (38) are connected to a negative medium voltage and the row lines (26) are connected to a positive medium voltage. To selectively erase one of the memory cells (24), the Column Line (28) associated with the programming side of the select memory cell transistor is connected to a positive medium voltage and the associated line (26) is connected to a positive Read voltage. The remaining Word Lines are connected to a negative Read voltage and the remaining Column Lines (28) are connected to a zero volt level.

摘要翻译： 低电压快闪EEPROM X-Cell包括构成非对称浮动栅极存储单元的存储单元晶体管阵列（24），其中仅在存储单元（24）的一侧实现编程。 每个存储器单元（24）的编程侧在节点（30）处连接到多个列线（28）中的一个。 每个节点（30）共享两个存储器单元（24）的两个存储器单元（24）的非编程侧的编程侧。 每个存储器单元（24）的控制栅极连接到与阵列的行相关联的字线（26）。 闪存写入所有存储单元（24），列线（38）连接到负中等电压，行线（26）连接到正中压。 为了选择性地擦除存储器单元（24）中的一个，与选择存储单元晶体管的编程侧相关联的列线（28）连接到正的中间电压，并且相关的线路（26）连接到正的读取电压 。 剩下的字线连接到负的读取电压，剩余的列线（28）连接到零伏电平。