公开(公告)号：US10509995B2

公开(公告)日：2019-12-17

申请号：US15090305

申请日：2016-04-04

Applicant: Micron Technology, Inc.

Inventor： Harold B Noyes ,  David R. Brown

IPC: G06N3/04 ,  G06F15/78 ,  G05B19/045 ,  G06N3/02 ,  G06F9/448

Abstract: A state machine engine having a program buffer. The program buffer is configured to receive configuration data via a bus interface for configuring a state machine lattice. The state machine engine also includes a repair map buffer configured to provide repair map data to an external device via the bus interface. The state machine lattice includes multiple programmable elements. Each programmable element includes multiple memory cells configured to analyze data and to output a result of the analysis.

公开(公告)号：US20190258592A1

公开(公告)日：2019-08-22

申请号：US16400739

申请日：2019-05-01

Applicant: Micron Technology, Inc.

Inventor： Debra Bell ,  Paul Glendenning ,  David R. Brown ,  Harold B Noyes

IPC: G06F13/12 ,  G06F13/40 ,  G06F13/28

Abstract: In one embodiment, a system includes a bus interface including a first processor, an indirect address storage storing a number of indirect addresses, and a direct address storage storing a number of direct addresses. The system also includes a number of devices connected to the bus interface and configured to analyze data. Each device of the number of devices includes a state machine engine. The bus interface is configured to receive a command from a second processor and to transmit an address for loading into the state machine engine of at least one device of the number of devices. The address includes a first address from the number of indirect addresses or a second address from the number of direct addresses.

公开(公告)号：US10339071B2

公开(公告)日：2019-07-02

申请号：US16192509

申请日：2018-12-10

Applicant: Micron Technology, Inc.

Inventor： Debra Bell ,  Paul Glendenning ,  David R. Brown ,  Harold B Noyes

IPC: G06F12/00 ,  G06F13/12 ,  G06F13/28 ,  G06F13/40

Abstract: In one embodiment, a system includes a bus interface including a first processor, an indirect address storage storing a number of indirect addresses, and a direct address storage storing a number of direct addresses. The system also includes a number of devices connected to the bus interface and configured to analyze data. Each device of the number of devices includes a state machine engine. The bus interface is configured to receive a command from a second processor and to transmit an address for loading into the state machine engine of at least one device of the number of devices. The address includes a first address from the number of indirect addresses or a second address from the number of direct addresses.

公开(公告)号：US20190164593A1

公开(公告)日：2019-05-30

申请号：US15826236

申请日：2017-11-29

Applicant: Micron Technology, Inc.

Inventor： Daniel B. Penney ,  David R. Brown ,  Gary L. Howe

IPC: G11C11/4093 ,  G11C11/4076

CPC classification number: G11C11/4093 ,  G11C7/1093 ,  G11C7/1096 ,  G11C11/4076 ,  G11C2207/2254

Abstract: A memory device includes a data write circuitry. The data write circuitry is configured to capture a first write command received via an external input/output (I/O) interface. The data write circuitry is further configured to generate a first internal write start (InternalWrStart) in a data strobe (DQS) domain after capture of the first write command. The data write circuitry is additionally configured to write a first one or more data bits into at least one memory bank based on the first InternalWrStart, wherein the first InternalWrStart is generated internally in the memory device.

公开(公告)号：US10157208B2

公开(公告)日：2018-12-18

申请号：US15357593

申请日：2016-11-21

Applicant: Micron Technology, Inc.

Inventor： Harold B Noyes ,  David R. Brown

IPC: G06F17/30 ,  G06F1/32 ,  G06K9/00

Abstract: Apparatuses and methods are provided for reducing power consumption in a pattern-recognition processor. A power control circuit may be coupled to a block of programmed state machines to enable selective activation and deactivation of the block during a pattern search. The block may be deactivated if the pattern search is no longer active in that block and activated when needed by the pattern search. Additionally, the block may be deactivated based on an identifier of the data stream being searched. Excess blocks not used for any programmed state machines may be disabled such that they are not refreshed during a memory cycle.

公开(公告)号：US20180341612A1

公开(公告)日：2018-11-29

申请号：US16053562

申请日：2018-08-02

Applicant: Micron Technology, Inc.

Inventor： David R. Brown ,  Harold B. Noyes ,  Inderjit S. Bains

IPC: G06F13/40 ,  G06F15/78 ,  G06F9/448 ,  G06N3/08

CPC classification number: G06F13/4027 ,  G06F9/4498 ,  G06F15/7867 ,  G06N3/08

Abstract: An apparatus can include a first state machine engine configured to receive a first portion of a data stream from a processor and a second state machine engine configured to receive a second portion of the data stream from the processor. The apparatus includes a buffer interface configured to enable data transfer between the first and second state machine engines. The buffer interface includes an interface data bus coupled to the first and second state machine engines. The buffer interface is configured to provide data between the first and second state machine engines.

公开(公告)号：US20180322006A1

公开(公告)日：2018-11-08

申请号：US16030479

申请日：2018-07-09

Applicant: Micron Technology, Inc.

Inventor： Harold B Noyes ,  David R. Brown ,  Paul Glendenning

IPC: G06F11/10 ,  H03M13/09

CPC classification number: G06F11/1004 ,  G06F11/1076 ,  H03M13/09

Abstract: Configuration content of electronic devices used for data analysis may be altered due to bit failure or corruption, for example. Accordingly, in one embodiment, a device includes a plurality of blocks, each block of the plurality of blocks includes a plurality of rows, each row of the plurality of rows includes a plurality of configurable elements, each configurable element of the plurality of configurable elements includes a data analysis element including a memory component programmed with configuration data. The data analysis element is configured to analyze at least a portion of a data stream based on the configuration data and to output a result of the analysis. The device also includes an error detection engine (EDE) configured to perform integrity validation of the configuration data.

公开(公告)号：US10067901B2

公开(公告)日：2018-09-04

申请号：US15683649

申请日：2017-08-22

Applicant: Micron Technology, Inc.

Inventor： David R. Brown ,  Harold B Noyes ,  Inderjit S. Bains

IPC: G06F17/00 ,  G06F13/40 ,  G06F15/78 ,  G06F9/448 ,  G06N3/08

Abstract: An apparatus can include a first state machine engine configured to receive a first portion of a data stream from a processor and a second state machine engine configured to receive a second portion of the data stream from the processor. The apparatus includes a buffer interface configured to enable data transfer between the first and second state machine engines. The buffer interface includes an interface data bus coupled to the first and second state machine engines. The buffer interface is configured to provide data between the first and second state machine engines.

公开(公告)号：US20170371811A1

公开(公告)日：2017-12-28

申请号：US15534978

申请日：2015-12-29

Applicant: Micron Technology, Inc.

Inventor： Harold B Noyes ,  David R. Brown ,  Paul Glendenning

IPC: G06F13/12 ,  G06F13/16 ,  G06F13/28 ,  G06F13/42

CPC classification number: G06F9/4498 ,  G06F13/126 ,  G06F13/1673 ,  G06F13/28 ,  G06F13/38 ,  G06F13/4282

Abstract: A device, includes an instruction buffer. The instruction buffer is configured to store instructions related to at least a portion of a data stream to be analyzed by a state machine engine as the device. The state machine engine includes configurable elements configured to analyze the at least a portion of a data stream and to selectively output the result of the analysis. Additionally, the instruction buffer is configured to receive the indications as part of a direct memory access (DMA) transfer.

公开(公告)号：US20170077930A1

公开(公告)日：2017-03-16

申请号：US15362232

申请日：2016-11-28

Applicant: Micron Technology, Inc.

Inventor： Harold B. Noyes ,  David R. Brown ,  Paul Glendenning ,  Irene J. Xu

IPC: H03K19/177 ,  G06F9/44 ,  H03K19/21

CPC classification number: H03K19/17708 ,  G05B19/045 ,  G06F7/00 ,  G06F9/4498 ,  G06F17/5054 ,  H03K19/0175 ,  H03K19/17704 ,  H03K19/20 ,  H03K19/21 ,  Y02T10/82

Abstract: Disclosed are methods and devices, among which is a device that includes a finite state machine lattice. The lattice may includes a programmable Boolean logic cell that may be programmed to perform various logic functions on a data stream. The programmability includes an inversion of a first input to the Boolean logic cell, an inversion of a last output of the Boolean logic cell, and a selection of an AND gate or an OR gate as a final output of the Boolean logic cell. The Boolean logic cell also includes end of data circuitry configured to cause the Boolean logic cell to only output after an end of data signifying the end of a data stream is received at the Boolean logic cell.

Abstract translation: 公开了方法和装置，其中包括有限状态机格的装置。 晶格可以包括可编程布尔逻辑单元，其可以被编程为在数据流上执行各种逻辑功能。 可编程性包括对布尔逻辑单元的第一输入的反转，布尔逻辑单元的最后输出的反转，以及选择与门或或门作为布尔逻辑单元的最终输出。 布尔逻辑单元还包括数据电路的结尾，该数据电路被配置为仅在布尔逻辑单元接收到表示数据流结束的数据结束后才输出布尔逻辑单元。