-
公开(公告)号：US12100438B2
公开(公告)日：2024-09-24
申请号：US17404487
申请日：2021-08-17
Applicant: Micron Technology, Inc.
Inventor： Dionisio Minopoli , Marco Sforzin , Daniele Balluchi
IPC: G11C7/04 , G11C11/406 , G11C11/4076
CPC classification number: G11C11/40626 , G11C11/40615 , G11C11/40622 , G11C11/4076
Abstract: A method including obtaining temperature values of at least one region of the non-volatile memory, each temperature value obtained at a given time instant, for each obtained temperature value at each given time instant, calculating the value of an operating function representative of an operating condition of the non-volatile memory, the value such operating function being time-dependent according to the temperature time-variation of such at least one region of the non-volatile memory, summing subsequent computed values of said operating function to obtain an accumulated value being representative of an elapsed fraction of a time limit associated with the at least one region of the non-volatile memory, comparing the accumulated value with a threshold value, and, based on said comparison, performing a management operation on the cells of the at least one region of the non-volatile memory when the accumulated value has a magnitude equal or greater than the threshold value.
-
公开(公告)号：US20240296094A1
公开(公告)日：2024-09-05
申请号：US18660954
申请日：2024-05-10
Applicant: Micron Technology, Inc.
Inventor： Paolo Amato , Marco Sforzin , Daniele Balluchi
CPC classification number: G06F11/1068 , G06F11/076 , G06F11/0772 , G06F11/1004
Abstract: Systems, apparatuses, and methods related to memory bank protection are described. A quantity of errors within a single memory bank is determined and the determined quantity can be used to further determine whether to access other memory banks to correct the determined quantity. The memory bank protection described herein avoids a single memory bank of a memory die being a single point of failure (SPOF).
-
公开(公告)号：US12079509B2
公开(公告)日：2024-09-03
申请号：US17868286
申请日：2022-07-19
Applicant: Micron Technology, Inc.
Inventor： Emanuele Confalonieri , Daniele Balluchi , Paolo Amato , Danilo Caraccio , Marco Sforzin
CPC classification number: G06F3/0655 , G06F3/0604 , G06F3/0679 , G06F11/1048
Abstract: A memory controller can include media controllers respectively coupled to memory devices. A first set of media controllers can be enabled during a first operating mode of the memory controller and a second set of media controller can be enabled during a second operating mode of the memory controller, during which some features, such as low-power features, can be disabled. Data accessed by each media controller of the first set can be aligned prior to being further transmitted to other circuitries of the memory controller that are dedicated, for example, for the low-power features.
-
公开(公告)号：US12074615B2
公开(公告)日：2024-08-27
申请号：US17969856
申请日：2022-10-20
Applicant: Micron Technology, Inc.
Inventor： Marco Sforzin , Paolo Amato , Yang Lu
CPC classification number: H03M13/152 , G06F13/4221 , H03M13/095
Abstract: Methods, systems, and devices related to mapping a plurality of pairs of bits of a memory transfer block (MTB) to a plurality of linked (LK) die input/output (LDIO) lines coupling a LK die to an interface (IF) die. The plurality of pairs of bits of the MTB can be communicated from the LK die to the IF die via the plurality of LDIO lines. Responsive to a failure of one of the plurality of LDIO lines, a Bose-Chaudhuri-Hocquenghem (BCH) error correction can be performed on the pairs of bits mapped to the failed LDIO line. Each of the plurality of pairs of bits is a respective symbol for the BCH error correction.
-
公开(公告)号：US20240194258A1
公开(公告)日：2024-06-13
申请号：US18586174
申请日：2024-02-23
Applicant: Micron Technology, Inc.
Inventor： Marco Sforzin , Paolo Amato , Innocenzo Tortorelli
CPC classification number: G11C13/0033 , G11C13/0004 , G11C13/0038 , G11C13/004 , G11C13/0069 , G11C29/021 , G11C29/12005
Abstract: A memory device can include a plurality of memory cells including a first group of memory cells and a second group of memory cells programmed to a predefined logic state. The plurality of memory cells includes a memory controller configured to apply a reading voltage to at least one selected memory cell of the first group during a reading operation, apply the reading voltage to the memory cells of the second group, and responsive to the logic state of at least one memory cell of the second group being assessed to be different from the predefined logic state perform a refresh operation of the memory cells of the first group by applying a recovery voltage higher than the reading voltage to assess the logic state thereof and reprogramming the memory cells of the first group to the logic state assessed with the recovery voltage.
-
Patent Agency Ranking
86.发明授权公开(公告)号：US12001706B2
公开(公告)日：2024-06-04
申请号：US17854639
申请日：2022-06-30
Applicant: Micron Technology, Inc.
Inventor： Marco Sforzin , Angelo Visconti , Giorgio Servalli , Daniele Balluchi , Paolo Amato
IPC: G06F3/06
CPC classification number: G06F3/0652 , G06F3/0616 , G06F3/0673
Abstract: Provided is a computing system including a memory system in communication with a host, to store data therein. The memory system includes a memory having a plurality of memory components coupled to the controller via a memory interface; and a memory controller configured to communicate with the memory to control data transmission and performing scrubbing operation of the memory components and detecting a region of the memory to be sanitized and performing a sanitization operation of the detected region to prevent the occurrence of failure.
-
公开(公告)号：US11994946B2
公开(公告)日：2024-05-28
申请号：US17752538
申请日：2022-05-24
Applicant: Micron Technology, Inc.
Inventor： Paolo Amato , Marco Sforzin , Daniele Balluchi
CPC classification number: G06F11/1068 , G06F11/076 , G06F11/0772 , G06F11/1004
Abstract: Systems, apparatuses, and methods related to memory bank protection are described. A quantity of errors within a single memory bank is determined and the determined quantity is used to further determine whether to access other memory banks to correct the determined quantity. The memory bank protection described herein avoids a single memory bank of a memory die being a single point of failure (SPOF).
-
公开(公告)号：US20240071486A1
公开(公告)日：2024-02-29
申请号：US17948520
申请日：2022-09-20
Applicant: Micron Technology, Inc.
Inventor： Marco Sforzin , Paolo Amato , Luca Barletta , Marco Pietro Ferrari , Antonino Favano
CPC classification number: G11C11/5642 , G11C5/147 , G11C11/5628
Abstract: The present disclosure includes apparatuses, methods, and systems for drift compensation for codewords in memory. An embodiment includes a memory device having an array of memory cells, and circuitry to sense a codeword stored in the array, determine a derivative value of a cell metric for each cell of the codeword based on a threshold voltage of that respective cell, a mean of threshold voltage values of each cell of the codeword, and a value proportional to a total quantity of the cells of the codeword and a position of the threshold voltage value of that respective cell in the threshold voltage values of each cell of the codeword, determine the cell metric for which the determined derivative value changes from a first polarity to a second polarity, input the determined cell metric to a Pearson detector, and determine originally programmed data of the codeword using the Pearson detector.
-
公开(公告)号：US11915750B2
公开(公告)日：2024-02-27
申请号：US17862391
申请日：2022-07-11
Applicant: Micron Technology, Inc.
Inventor： Marco Sforzin , Paolo Amato , Innocenzo Tortorelli
CPC classification number: G11C13/0033 , G11C13/0004 , G11C13/004 , G11C13/0038 , G11C13/0069 , G11C29/021 , G11C29/12005
Abstract: A memory device can include a plurality of memory cells including a first group of memory cells and a second group of memory cells programmed to a predefined logic state. The plurality of memory cells includes a memory controller configured to apply a reading voltage to at least one selected memory cell of the first group during a reading operation, apply the reading voltage to the memory cells of the second group, and responsive to the logic state of at least one memory cell of the second group being assessed to be different from the predefined logic state perform a refresh operation of the memory cells of the first group by applying a recovery voltage higher than the reading voltage to assess the logic state thereof and reprogramming the memory cells of the first group to the logic state assessed with the recovery voltage.
-
公开(公告)号：US20240004751A1
公开(公告)日：2024-01-04
申请号：US18216254
申请日：2023-06-29
Applicant: Micron Technology, Inc.
Inventor： Marco Sforzin , John D. Porter
IPC: G06F11/10
CPC classification number: G06F11/10
Abstract: An on-die controller can provide an error correction capability for data stored in an array of memory cells located on the same die as the on-die controller. The error correction capability provided by the on-die controller eliminates a need to transfer error correction code (ECC) data to an external controller that may have provided the error correction capability in lieu of the on-die controller, which can provide more channel bandwidth for other types of non-user data for further strengthening data reliability, security, integrity of the memory system.
-
-
-
-
-
-
-
-
-
Search Results
216
records
(took 0.023 seconds)
