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    Integrated assemblies and methods of forming integrated assemblies
    82.
    发明授权
    Integrated assemblies and methods of forming integrated assemblies 有权

    公开(公告)号：US10546848B2

    公开(公告)日：2020-01-28

    申请号：US16398433

    申请日：2019-04-30

    Applicant: Micron Technology, Inc.

    Inventor： Daniel Billingsley ,  Everett A. McTeer ,  Christopher W. Petz ,  Haoyu Li ,  John Mark Meldrim ,  Yongjun Jeff Hu

    IPC: G11C11/34 ,  H01L27/02 ,  H01L21/82 ,  H01L27/12 ,  G11C5/06 ,  H01L23/532

    Abstract: An integrated assembly includes an insulative mass with a first region adjacent to a second region. The first region has a greater amount of one or more inert interstitial elements incorporated therein than does the second region. Some embodiments include an integrated assembly which has vertically-extending channel material pillars, and which has memory cells along the channel material pillars. A conductive structure is under the channel material pillars. The conductive structure includes doped semiconductor material in direct contact with bottom regions of the channel material pillars. An insulative mass is along the bottom regions of the channel material pillars. The insulative mass has an upper region over a lower region. The lower region has a greater amount of one or more inert interstitial elements incorporated therein than does the upper region. Some embodiments include methods of forming integrated assemblies.

    Methods of forming NAND cell units and NAND cell units
    83.
    发明授权
    Methods of forming NAND cell units and NAND cell units 有权

    公开(公告)号：US10529834B2

    公开(公告)日：2020-01-07

    申请号：US15967457

    申请日：2018-04-30

    Applicant: Micron Technology, Inc.

    Inventor： Yongjun Jeff Hu

    IPC: H01L29/66 ,  H01L21/28 ,  H01L27/11521 ,  H01L27/11524 ,  H01L29/423 ,  H01L29/792 ,  H01L27/115 ,  H01L27/1157

    Abstract: Some embodiments include methods of forming charge storage transistor gates and standard FET gates in which common processing is utilized for fabrication of at least some portions of the different types of gates. FET and charge storage transistor gate stacks may be formed. The gate stacks may each include a gate material, an insulative material, and a sacrificial material. The sacrificial material is removed from the FET and charge storage transistor gate stacks. The insulative material of the FET gate stacks is etched through. A conductive material is formed over the FET gate stacks and over the charge storage transistor gate stacks. The conductive material physically contacts the gate material of the FET gate stacks, and is separated from the gate material of the charge storage transistor gate stacks by the insulative material remaining in the charge storage transistor gate stacks. Some embodiments include gate structures.

    Methods of forming memory cells and semiconductor devices
    84.
    发明授权
    Methods of forming memory cells and semiconductor devices 有权

    公开(公告)号：US10418554B2

    公开(公告)日：2019-09-17

    申请号：US16172260

    申请日：2018-10-26

    Applicant: Micron Technology, Inc.

    Inventor： Tsz W. Chan ,  D. V. Nirmal Ramaswamy ,  Qian Tao ,  Yongjun Jeff Hu ,  Everett A. McTeer

    IPC: H01L45/00 ,  H01L27/24

    Abstract: A memory cell comprising a threshold switching material over a first electrode on a substrate. The memory cell includes a second electrode over the threshold switching material and at least one dielectric material between the threshold switching material and at least one of the first electrode and the second electrode. A memory material overlies the second electrode. The dielectric material may directly contact the threshold switching material and each of the first electrode and the second electrode. Memory cells including only one dielectric material between the threshold switching material and an electrode are disclosed. A memory device including the memory cells and methods of forming the memory cells are also described.

    Assemblies having vertically-extending structures
    85.
    发明授权
    Assemblies having vertically-extending structures 有权

    公开(公告)号：US10355014B1

    公开(公告)日：2019-07-16

    申请号：US15852989

    申请日：2017-12-22

    Applicant: Micron Technology, Inc.

    Inventor： David Ross Economy ,  John Mark Meldrim ,  Haoyu Li ,  Yongjun Jeff Hu ,  Christopher W. Petz ,  Daniel Billingsley ,  Everett A. McTeer

    IPC: H01L27/11582 ,  H01L27/11556 ,  H01L27/11519 ,  H01L21/311 ,  H01L27/11565 ,  H01L21/768

    Abstract: Some embodiments include an assembly which has channel material pillars, and which has memory cells along the channel material pillars. A conductive structure is under the channel material pillars. The conductive structure has doped semiconductor material in direct contact with bottom regions of the channel material pillars. One or more of magnesium, scandium, yttrium and lanthanide elements is along the bottom regions of the channel material pillars. Some embodiments include methods of forming assemblies. A structure is formed, and a mass is formed against an upper surface of the structure. Plugs are formed within openings in the mass. The plugs comprise a second material over a first material. The first material includes one or more of magnesium, scandium, yttrium and lanthanide elements. Openings are formed to terminate on the first material, and are then extended through the first material. Channel material pillars are formed within the openings.

    Semiconductor devices
    89.
    发明授权
    Semiconductor devices 有权
    半导体器件

    公开(公告)号：US09530842B2

    公开(公告)日：2016-12-27

    申请号：US14597766

    申请日：2015-01-15

    Applicant: Micron Technology, Inc.

    Inventor： Shu Qin ,  Yongjun Jeff Hu ,  Allen McTeer

    IPC: H01L29/76 ,  H01L29/08 ,  H01L29/45 ,  H01L21/223 ,  H01L27/092

    CPC classification number: H01L29/0847 ,  H01L21/2236 ,  H01L21/28518 ,  H01L21/76814 ,  H01L21/76825 ,  H01L21/823418 ,  H01L27/092 ,  H01L29/456 ,  H01L29/665

    Abstract: Some embodiments include a device having an n-type diffusion region, and having a boron-doped region within the n-type diffusion region. The boron-doped region extends no deeper than about 10 nanometers from an upper surface of the n-type diffusion region. Some embodiments include a method in which first boron-enhanced regions are formed within upper portions of n-type source/drain regions of an NMOS (n-type metal-oxide-semiconductor) device and second boron-enhanced regions are simultaneously formed within upper portions of p-type source/drain regions of a PMOS (p-type metal-oxide-semiconductor) device. The first and second boron-enhanced regions extend to depths of less than or equal to about 10 nanometers.

    Abstract translation: 一些实施例包括具有n型扩散区的器件，并且在n型扩散区内具有硼掺杂区。 硼掺杂区从n型扩散区的上表面延伸不超过约10纳米。 一些实施例包括其中在NMOS（n型金属氧化物半导体）器件的n型源极/漏极区的上部形成第一硼增强区的方法，并且第二硼增强区同时形成在上部 PMOS（p型金属氧化物半导体）器件的p型源/漏区的部分。 第一和第二硼增强区域延伸到小于或等于约10纳米的深度。

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