公开(公告)号：US06475867B1

公开(公告)日：2002-11-05

申请号：US09824416

申请日：2001-04-02

申请人： Angela T. Hui ,  Kouros Ghandehari ,  Bhanwar Singh

发明人： Angela T. Hui ,  Kouros Ghandehari ,  Bhanwar Singh

IPC分类号： H07L21336

CPC分类号： H01L21/31144 ,  H01L21/0337 ,  H01L21/0338

摘要： An exemplary method of forming integrated circuit device features by oxidization of titanium hard mask is described. This method can include providing a photoresist pattern of photoresist features over a first layer of material deposited over a second layer of material; etching the first layer of material according to the photoresist pattern to form material features; oxidizing exposed portions of the material features where the material features are made of a material which expands during oxidation; and etching the second layer of material according to the material features which have expanded as a result of oxidation. Advantageously, the expansion of the material features results in a smaller distance between material features than the distance between photoresist features.

摘要翻译： 描述了通过钛硬掩模的氧化形成集成电路器件特征的示例性方法。 该方法可以包括在沉积在第二材料层上的第一材料层上提供光致抗蚀剂特征的光致抗蚀剂图案; 根据光致抗蚀剂图案蚀刻第一层材料以形成材料特征; 氧化材料特征的暴露部分，其中材料特征由在氧化期间膨胀的材料制成; 并根据由于氧化而膨胀的材料特征蚀刻第二层材料。 有利地，材料特征的扩展导致材料特征之间的距离比光致抗蚀剂特征之间的距离更小。

公开(公告)号：US06465835B1

公开(公告)日：2002-10-15

申请号：US09487964

申请日：2000-01-18

申请人： Tuan Duc Pham ,  Mark T. Ramsbey ,  Sameer S. Haddad ,  Angela T. Hui

发明人： Tuan Duc Pham ,  Mark T. Ramsbey ,  Sameer S. Haddad ,  Angela T. Hui

IPC分类号： H01L29788

CPC分类号： H01L27/11526 ,  H01L27/105 ,  H01L27/11543

摘要： An improved flash memory device having core stacks and periphery stacks which are protected by first and second thin side walls, side spacers over the side walls, and an HTO layer over the stacks, and side spacer. The flash memory device has an intermetallic dielectric layer placed over the HTO layer. A tungsten plug is placed in the intermetallic dielectric layer to provide an electrical connection to the drain of the flash memory device. The additional first and second side walls reduce current leakage between core stacks and the tungsten plug and help to protect the stacks during fabrication.

摘要翻译： 具有由第一和第二薄侧壁，侧壁上的侧隔离物以及叠层上的HTO层和侧隔板保护的芯堆叠和外围堆叠的改进的闪存器件。 闪存器件具有置于HTO层上的金属间介电层。 将钨塞放置在金属间介电层中以提供与闪存器件的漏极的电连接。 附加的第一和第二侧壁减小了芯堆叠和钨插头之间的电流泄漏，并有助于在制造期间保护堆叠。

公开(公告)号：US06461923B1

公开(公告)日：2002-10-08

申请号：US09639816

申请日：2000-08-17

申请人： Angela T. Hui ,  Paul R. Besser ,  Susan H. Chen

发明人： Angela T. Hui ,  Paul R. Besser ,  Susan H. Chen

IPC分类号： H01L21336

CPC分类号： H01L21/2652 ,  H01L21/28518 ,  H01L29/665 ,  H01L29/6659

摘要： Sub-micron dimensioned, ultra-shallow junction MOS and/or CMOS transistor devices having reduced or minimal junction leakage are formed by a salicide process wherein silicon substrate surfaces intended to be subjected to ion implantation for source/drain formation are protected from damage resulting from reactive plasma etching of a blanket insulative layer for sidewall spacer formation by leaving a residual thickness of the insulative layer thereon. The residual layer is retained during ion implantation and removed prior to salicide processing to provide an undamaged surface for optimal contact formation thereon. Embodiments include anisotropically plasma etching a major amount of the thickness of the blanket insulative layer during a preselected interval for sidewall spacer formation and removing the residual thickness thereof after source/drain implantation by etching with dilute aqueous HF.

摘要翻译： 通过自对准硅化物工艺形成具有减小的或最小的结漏电的亚微米尺寸的超浅结MOS和/或CMOS晶体管器件，其中旨在进行用于源极/漏极形成的离子注入的硅衬底表面被保护免受由 通过在其上留下绝缘层的剩余厚度来进行用于侧壁间隔物形成的覆盖绝缘层的反应等离子体蚀刻。 残留层在离子注入期间被保留，并且在自对准硅化物处理之前被去除以提供未损坏的表面以在其上形成最佳的接触形成。 实施例包括在用于侧壁间隔物形成的预选间隔期间各向异性等离子体蚀刻绝缘层的厚度的主要量，并且通过用稀HF水溶液蚀刻去除其源极/漏极注入之后的剩余厚度。

公开(公告)号：US06431182B1

公开(公告)日：2002-08-13

申请号：US09427861

申请日：1999-10-27

申请人： Mohammad R. Rakhshandehroo ,  Mark S. Chang ,  Angela T. Hui

发明人： Mohammad R. Rakhshandehroo ,  Mark S. Chang ,  Angela T. Hui

IPC分类号： B08B600

CPC分类号： H01L21/02063 ,  H01L21/31116 ,  H01L21/31138 ,  H01L21/76814

摘要： A method and article of manufacture of a via in a semiconductor layered device. The method can include applying an OH/H containing plasma, such as H2O or O2 or a forming gas, to a via which has been etched in a layer of the device. A mixture of oxygen and fluorine-based plasma is applied to complete cleaning of the via to provide a clean via with very little loss of dimensional and surface quality. In another aspect the OH/H containing plasma and the oxygen and fluorine-based plasma are applied together to clean the via.

摘要翻译： 半导体分层器件中的通孔的制造方法和制造方法。 该方法可以包括将OH / H等离子体（例如H 2 O或O 2或形成气体）施加到在器件的层中被蚀刻的通孔。 施加氧和氟基等离子体的混合物以完成通孔的清洁以提供清洁的通孔，其尺寸和表面质量几乎没有损失。 另一方面，将包含OH / H的等离子体和基于氧和氟的等离子体一起施加以清洁通孔。

公开(公告)号：US08652907B2

公开(公告)日：2014-02-18

申请号：US13071385

申请日：2011-03-24

申请人： Chuan Lin ,  Hidehiko Shiraiwa ,  Bradley Marc Davis ,  Lei Xue ,  Simon S. Chan ,  Kenichi Ohtsuka ,  Angela T. Hui ,  Scott Allan Bell

发明人： Chuan Lin ,  Hidehiko Shiraiwa ,  Bradley Marc Davis ,  Lei Xue ,  Simon S. Chan ,  Kenichi Ohtsuka ,  Angela T. Hui ,  Scott Allan Bell

IPC分类号： H01L21/28 ,  H01L21/8234

CPC分类号： H01L29/4916 ,  H01L21/28044 ,  H01L21/823456 ,  H01L27/11543 ,  H01L27/11546 ,  H01L29/78

摘要： A method of fabricating an integrated circuit including a first region and a second region each having different poly-silicon gate structures is provided. The method includes depositing a first poly-silicon layer over the first and the second region and depositing, within the second region, an oxide layer over the first poly-silicon layer. A second poly-silicon layer is deposited over the first poly-silicon layer and the oxide region. A portion of the second poly-silicon layer that lies over the oxide region is then stripped away.

摘要翻译： 提供一种制造集成电路的方法，该集成电路包括具有不同多晶硅栅极结构的第一区域和第二区域。 该方法包括在第一和第二区域上沉积第一多晶硅层，并在第二区域内在第一多晶硅层上沉积氧化物层。 在第一多晶硅层和氧化物区域上沉积第二多晶硅层。 然后剥离位于氧化物区域上方的第二多晶硅层的一部分。

公开(公告)号：US20120241871A1

公开(公告)日：2012-09-27

申请号：US13071385

申请日：2011-03-24

申请人： Chuan Lin ,  Hidehiko Shiraiwa ,  Bradley Marc Davis ,  Lei Xue ,  Simon S. Chan ,  Kenichi Ohtsuka ,  Angela T. Hui ,  Scott Allan Bell

发明人： Chuan Lin ,  Hidehiko Shiraiwa ,  Bradley Marc Davis ,  Lei Xue ,  Simon S. Chan ,  Kenichi Ohtsuka ,  Angela T. Hui ,  Scott Allan Bell

IPC分类号： H01L29/788 ,  H01L21/28

CPC分类号： H01L29/4916 ,  H01L21/28044 ,  H01L21/823456 ,  H01L27/11543 ,  H01L27/11546 ,  H01L29/78

摘要： A method of fabricating an integrated circuit including a first region and a second region each having different poly-silicon gate structures is provided. The method includes depositing a first poly-silicon layer over the first and the second region and depositing, within the second region, an oxide layer over the first poly-silicon layer. A second poly-silicon layer is deposited over the first poly-silicon layer and the oxide region. A portion of the second poly-silicon layer that lies over the oxide region is then stripped away.

摘要翻译： 提供一种制造集成电路的方法，该集成电路包括具有不同多晶硅栅极结构的第一区域和第二区域。 该方法包括在第一和第二区域上沉积第一多晶硅层，并在第二区域内在第一多晶硅层上沉积氧化物层。 在第一多晶硅层和氧化物区域上沉积第二多晶硅层。 然后剥离位于氧化物区域上方的第二多晶硅层的一部分。

公开(公告)号：US08067314B2

公开(公告)日：2011-11-29

申请号：US12424023

申请日：2009-04-15

申请人： Bradley M. Davis ,  Jihwan Choi ,  Angela T. Hui

发明人： Bradley M. Davis ,  Jihwan Choi ,  Angela T. Hui

IPC分类号： H01L21/76

CPC分类号： H01L21/32139 ,  H01L21/0337 ,  H01L21/28132 ,  H01L21/823456

摘要： Disclosed are methods and devices for targeting CD of selected transistors in a semiconductor device. Varying CD is done by forming hard mask lines in a hard mask layer that have varying amounts of spacer material associated therewith. Hard mask lines corresponding to selected transistors are either left covered or uncovered by a resist applied over the hard mask layer. Then, spacer material is selectively removed from the hard mask lines to vary the width of hard mask lines and associated side wall spacers. A gate layer is then etched through the spaces in the hard mask lines to form gate lines having varying widths and targeted CD.

摘要翻译： 公开了用于在半导体器件中靶向所选晶体管的CD的方法和装置。 通过在硬掩模层中形成具有不同量的与其相关联的间隔物材料的硬掩模线来完成不同的CD。 对应于所选择的晶体管的硬掩模线被被涂覆在硬掩模层上的抗蚀剂覆盖或未覆盖。 然后，从硬掩模线选择性地去除间隔物材料以改变硬掩模线和相关联的侧壁间隔物的宽度。 然后通过硬掩模线中的空间蚀刻栅极层以形成具有不同宽度的栅极线和目标CD。

公开(公告)号：US07972951B2

公开(公告)日：2011-07-05

申请号：US12688477

申请日：2010-01-15

申请人： Angela T. Hui ,  Jihwan Choi

发明人： Angela T. Hui ,  Jihwan Choi

IPC分类号： H01L21/3205 ,  H01L21/4763

CPC分类号： H01L21/31116 ,  H01L21/31138 ,  H01L21/31144 ,  H01L21/32136 ,  H01L21/32137 ,  H01L27/115 ,  H01L27/11521 ,  H01L27/11568

摘要： A method of manufacturing a memory device forms a first dielectric layer over a substrate, forms a charge storage layer over the first dielectric layer, forms a second dielectric layer over the charge storage layer, and forms a control gate layer over the second dielectric layer. The method also forms a hard mask layer over the control gate layer, forms a bottom anti-reflective coating (BARC) layer over the hard mask layer, and provides an etch chemistry that includes tetrafluoromethane (CF4) and trifluoromethane (CHF3) to etch at least the control gate layer.

摘要翻译： 一种制造存储器件的方法在衬底上形成第一介电层，在第一介电层之上形成电荷存储层，在电荷存储层上形成第二介电层，并在第二介电层上形成控制栅极层。 该方法还在控制栅极层上形成硬掩模层，在硬掩模层上形成底部抗反射涂层（BARC）层，并提供包括四氟甲烷（CF4）和三氟甲烷（CHF 3）在内的蚀刻化学品，以蚀刻 至少控制门层。

公开(公告)号：US20100264519A1

公开(公告)日：2010-10-21

申请号：US12424023

申请日：2009-04-15

申请人： Bradley M. Davis ,  Jihwan Choi ,  Angela T. Hui

发明人： Bradley M. Davis ,  Jihwan Choi ,  Angela T. Hui

IPC分类号： H01L29/423 ,  H01L21/306

CPC分类号： H01L21/32139 ,  H01L21/0337 ,  H01L21/28132 ,  H01L21/823456

摘要： Disclosed are methods and devices for targeting CD of selected transistors in a semiconductor device. Varying CD is done by forming hard mask lines in a hard mask layer that have varying amounts of spacer material associated therewith. Hard mask lines corresponding to selected transistors are either left covered or uncovered by a resist applied over the hard mask layer. Then, spacer material is selectively removed from the hard mask lines to vary the width of hard mask lines and associated side wall spacers. A gate layer is then etched through the spaces in the hard mask lines to form gate lines having varying widths and targeted CD.

摘要翻译： 公开了用于在半导体器件中靶向所选晶体管的CD的方法和装置。 通过在硬掩模层中形成具有不同量的与其相关联的间隔物材料的硬掩模线来完成不同的CD。 对应于所选择的晶体管的硬掩模线被被涂覆在硬掩模层上的抗蚀剂覆盖或未覆盖。 然后，从硬掩模线选择性地去除间隔物材料以改变硬掩模线和相关联的侧壁间隔物的宽度。 然后通过硬掩模线中的空间蚀刻栅极层以形成具有不同宽度的栅极线和目标CD。

公开(公告)号：US07670959B2

公开(公告)日：2010-03-02

申请号：US11616085

申请日：2006-12-26

申请人： Angela T. Hui ,  Jihwan Choi

发明人： Angela T. Hui ,  Jihwan Choi

IPC分类号： H01L21/302 ,  H01L21/461

CPC分类号： H01L21/31116 ,  H01L21/31138 ,  H01L21/31144 ,  H01L21/32136 ,  H01L21/32137 ,  H01L27/115 ,  H01L27/11521 ,  H01L27/11568

摘要： A method of manufacturing a memory device forms a first dielectric layer over a substrate, forms a charge storage layer over the first dielectric layer, forms a second dielectric layer over the charge storage layer, and forms a control gate layer over the second dielectric layer. The method also forms a hard mask layer over the control gate layer, forms a bottom anti-reflective coating (BARC) layer over the hard mask layer, and provides an etch chemistry that includes tetrafluoromethane (CF4) and trifluoromethane (CHF3) to etch at least the control gate layer.

摘要翻译： 一种制造存储器件的方法在衬底上形成第一介电层，在第一介电层之上形成电荷存储层，在电荷存储层上形成第二介电层，并在第二介电层上形成控制栅极层。 该方法还在控制栅极层上形成硬掩模层，在硬掩模层上形成底部抗反射涂层（BARC）层，并提供包括四氟甲烷（CF4）和三氟甲烷（CHF 3）在内的蚀刻化学品，以蚀刻 至少控制门层。